Semiconductor packages and methods for forming the same

Abstract

Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and into scribe line regions. In some embodiments, heterogeneous integrated circuit dies with edge interconnect features are fabricated on the same substrate. Edge interconnect features of the neighboring integrated circuit dies are connected to each other and provide direct connections between the integrated circuit dies without going through an interposer.

1 . A semiconductor device, comprising:
 a first integrated circuit die comprising a first sealing ring encircling a first circuit region;   a second integrated circuit die comprising a second sealing ring encircling a second circuit region;   a dielectric layer formed between the first sealing ring and the second sealing ring; and   a conductive line extending from the first circuit region to the second circuit region through the first sealing ring, the dielectric layer, and the second sealing ring.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first integrated circuit die further comprises a first interconnect structure, and the conductive line is connected to the first interconnect structure. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the first interconnect structure comprises:
 an IMD (inter metal dielectric) layer; and   a conductive feature embedded in the IMD layer, wherein the conductive line is connected to the conductive feature.   
     
     
         4 . The semiconductor device of  claim 3 , wherein the conductive line extends between sections of the first sealing ring. 
     
     
         5 . The semiconductor device of  claim 1 , further comprising a substrate, wherein the first integrated circuit die, the dielectric layer and the second integrated circuit die are formed on the substrate. 
     
     
         6 . The semiconductor device of  claim 2 , wherein the first integrated circuit die further comprises a plurality of external contacts formed on the first interconnect structure. 
     
     
         7 . The semiconductor device of  claim 6 , further comprising an interposer substrate attached to the plurality of external contacts of the first integrated circuit die. 
     
     
         8 . An integrated circuit die, comprising:
 a device layer comprising one or more semiconductor devices;   an interconnect structure formed on the device layer, wherein the interconnect structure comprises:
 a dielectric layer; 
 a sealing ring formed in the dielectric layer encircling a circuit region within the dielectric layer; and 
 one or more conductive features embedded in the circuit region of the dielectric layer, wherein the one or more conductive features are connected to one or more semiconductor devices in the device layer; and 
   a plurality of edge interconnect features formed in the dielectric layer, wherein the plurality of edge interconnect features extending outwards from the circuit region through the sealing ring.   
     
     
         9 . The integrated circuit die of  claim 8 , wherein at least a portion of the plurality of edge interconnect features are electrically connected to the one or more conductive features. 
     
     
         10 . The integrated circuit die of  claim 9 , wherein the sealing ring is a rectangle ring, and the plurality of edge interconnect features are symmetrically distributed along four sides of the rectangle ring. 
     
     
         11 . The integrated circuit die of  claim 10 , wherein a portion of the dielectric layer is formed outside the sealing ring, and the plurality of edge interconnect features extend across the sealing ring. 
     
     
         12 . The integrated circuit die of  claim 8 , wherein the plurality of edge interconnect features extending between sections of the sealing ring. 
     
     
         13 . The integrated circuit die of  claim 8 , wherein the interconnect structure further comprises a second dielectric layer, and a second plurality of edge interconnect features formed in the second dielectric layer. 
     
     
         14 . The integrated circuit die of  claim 8 , wherein the plurality of edge interconnect features are connected to conductive features in a neighboring integrated circuit die. 
     
     
         15 . A semiconductor package, comprising:
 a first integrated circuit die and a second integrated circuit die formed on a substrate and divided by a scribe line, wherein the first integrated circuit die has a first edge interconnect feature, and the second integrated circuit die has a second edge interconnect feature, and the first edge interconnect feature are connected to the second edge interconnect feature across the scribe line; and   a printed circuit board, wherein with the first and second circuit dies are bonded to the printed circuit board while remaining connected to each other at the scribe line.   
     
     
         16 . The semiconductor package of  claim 15 , wherein each of the first and second integrated circuit dies comprises:
 a device layer including one or more semiconductor devices; and   an interconnect structure over the device layer, wherein the interconnect structure includes one or more IMD layers, and the first and second edge interconnect features are embedded in the one or more IMD layers.   
     
     
         17 . The semiconductor package of  claim 16 , wherein each of the first and second integrated circuit dies further comprises:
 one or more sealing rings surrounding the interconnect structure, wherein the first edge interconnect feature and the second edge interconnect feature extend through the one or more sealing rings.   
     
     
         18 . The semiconductor package of  claim 15 , further comprising
 an interposer bonded to the first and second integrated circuit dies through plurality of external contacts.   
     
     
         19 . The semiconductor package of  claim 15 , wherein the first integrated circuit die includes comprises a plurality of edge interconnect features symmetrically distributed along four edges of the first integrated circuit die, and the second circuit die is disposed along a first edge of the four edges of the first integrated circuit die. 
     
     
         20 . The semiconductor package of  claim 19 , further comprising:
 a third integrated circuit die disposed along a second edge of the four edges of the first integrated circuit die, wherein at one of the plurality of first edge interconnect features extends from the first die to the third integrated circuit die.