Different Source/Drain Profiles for N-type FinFETs and P-type FinFETs

Abstract

A method includes etching a first and a second semiconductor fin to form a first and a second recesses, epitaxially growing an n-type source/drain region comprising a first portion and a second portion from the first and the second recesses, and a first middle portion in between and having a concave top surface. A first contact opening is formed extending into the n-type source/drain region and having a first V-shaped bottom. The method further includes etching a third and a fourth semiconductor fin to form a third and a fourth recesses, and forming a p-type source/drain region including a third portion and a third portion grown from the third and the fourth recesses, and a second middle portion in between and having a convex top surface. A second contact opening is formed and has a second V-shaped bottom, with a tip of the second V-shaped bottom being downwardly pointing.

What is claimed is: 
     
         1 . A device comprising:
 a first semiconductor strip and a second semiconductor strip;   an n-type Fin-Field Effect Transistor (FinFET) comprising:
 an n-type source/drain region comprising:
 a first layer comprising a first portion and a second portion overlapping the first semiconductor strip and the second semiconductor strip, respectively, and a first middle portion joined to the first portion and the second portion, with a first void being under and exposed to the first layer; and 
 a second layer over and contacting the first layer and comprising a concave top surface, wherein the second layer is separated from the first void by the first layer; 
 
   a third semiconductor strip and a fourth semiconductor strip; and   a p-type FinFET comprising:
 a p-type source/drain region comprising:
 a third layer comprising a third portion and a fourth portion overlapping the third semiconductor strip and the fourth semiconductor strip, respectively, wherein the third portion and the fourth portion are spaced apart from each other, with a second void being formed under and exposed to the third layer; and 
 a fourth layer over the third layer, wherein a bottom surface of the fourth layer is exposed to the second void, and the fourth layer comprises a convex top surface. 
 
   
     
     
         2 . The device of  claim 1  further comprising:
 first fin spacers on opposing sides of the first semiconductor strip, wherein the n-type source/drain region further comprises a fifth layer underlying and contacting the first layer, and wherein a first top surface of the fifth layer is lower than second top surfaces of the first fin spacers. 
 
     
     
         3 . The device of  claim 1 , wherein the fourth layer comprises:
 an additional p-type layer, and a p-type capping layer over and contacting the additional p-type layer, wherein the additional p-type layer and the p-type capping layer have different compositions.   
     
     
         4 . The device of  claim 3 , wherein the n-type FinFET further comprises a gate stack, and the p-type capping layer comprises:
 a first part having a first lateral distance from the gate stack;   a second part having a second lateral distance from the gate stack, with the second lateral distance being greater than the first lateral distance;   a contact plug penetrating through the second part; and   a first silicide layer underlying the contact plug, wherein the first silicide layer has a first additional concave top surface.   
     
     
         5 . The device of  claim 4 , wherein the first part has the convex top surface. 
     
     
         6 . The device of  claim 4 , wherein the first additional concave top surface is viewed from a vertical plane that is parallel to a lengthwise direction of the gate stack. 
     
     
         7 . The device of  claim 4  further comprising:
 a second silicide layer on the p-type source/drain region, wherein the second silicide layer has a second additional concave top surface. 
 
     
     
         8 . The device of  claim 1 , wherein the n-type source/drain region comprises:
 a first outer portion on a first outer side of the first semiconductor strip; and   a first inner portion between the first semiconductor strip and the second semiconductor strip, wherein the first semiconductor strip and the second semiconductor strip are immediately neighboring each other, and wherein the first outer portion is narrow than a half of the first inner portion.   
     
     
         9 . The device of  claim 8 , wherein the p-type source/drain region comprises:
 a second outer portion on a second outer side of the third semiconductor strip; and   a second inner portion between the third semiconductor strip and the fourth semiconductor strip, wherein the second outer portion is wider than a half of the second inner portion.   
     
     
         10 . The device of  claim 1 , wherein each the p-type source/drain region and the n-type source/drain region comprises three semiconductor layers. 
     
     
         11 . A device comprising:
 an n-type Fin-Field Effect Transistor (FinFET) comprising:
 a first gate stack; and 
 an n-type source/drain region comprising:
 a first portion comprising a first concave top surface; 
 a second portion, with the first portion being between the first gate stack and the first portion; 
 a first contact plug extend into the second portion; and 
 a first silicide layer under the first contact plug, wherein the first silicide layer has a second concave top surface; and 
 
   a p-type FinFET comprising:
 a second gate stack; and 
 an p-type source/drain region comprising:
 a third portion comprising a convex top surface; 
 a fourth portion, with the third portion being between the second gate stack and the third portion; 
 a second contact plug extend into the fourth portion; and 
 a second silicide layer under the second contact plug, wherein the second silicide layer has a third concave top surface. 
 
   
     
     
         12 . The device of  claim 11  further comprising:
 a contact etch stop layer on the n-type source/drain region and the p-type source/drain region, wherein the contact etch stop layer comprises a vertical portion contacting the third portion of the p-type source/drain region to form a vertical interface. 
 
     
     
         13 . The device of  claim 11 , wherein the n-type source/drain region comprises:
 a first epitaxy layer, wherein the first epitaxy layer comprises a first part, a second part, and a middle part joining the first part to the second part, wherein the first part, the second part and the middle part are formed of a same material;   a first void overlapped by the middle part, with a bottom surface of the first epitaxy layer being exposed to the first void; and   a second epitaxy layer and contacting the first epitaxy layer, wherein a top surface of the second epitaxy layer contacts the first silicide layer.   
     
     
         14 . The device of  claim 13 , wherein the p-type source/drain region comprises:
 a third epitaxy layer comprising a third part and a fourth part separated from the third part;   a fourth epitaxy layer over the third epitaxy layer and connecting the third part to the fourth part; and   a second void, wherein bottom surfaces of the third epitaxy layer, the third part, and the fourth part are exposed to the second void.   
     
     
         15 . The device of  claim 11 , wherein the first concave top surface and the second concave top surface are viewed from a first vertical plane that is parallel to a first lengthwise direction of the first gate stack, and the convex top surface and the third concave top surface are viewed from a second vertical plane that is parallel to a second lengthwise direction of the second gate stack. 
     
     
         16 . The device of  claim 11 , wherein the first contact plug penetrates through a first capping layer of the n-type source/drain region, and the second contact plug penetrates through a second capping layer of the p-type source/drain region. 
     
     
         17 . The device of  claim 16 , wherein the first capping layer comprises SiGeP, and the second capping layer comprises SiGeB. 
     
     
         18 . A device comprising:
 a first gate stack;   an n-type source/drain region comprising:
 a first portion and a second portion; and 
 a first middle portion between the first portion and the second portion, wherein the first middle portion has a first concave top surface, wherein the first concave top surface is viewed from a first vertical plane that is parallel to a first lengthwise direction of the first gate stack; 
   a first contact plug, with the first vertical plane being between the first contact plug and the first gate stack;   a first silicide layer underlying the first contact plug and in the n-type source/drain region, wherein the first silicide layer comprises a second concave top surface;   a second gate stack;   a p-type source/drain region comprising:
 a third portion and a fourth portion; and 
 a second middle portion between the third portion and the fourth portion, wherein the second middle portion has a convex top surface, and wherein the convex top surface is viewed from a second vertical plane that is parallel to a second lengthwise direction of the second gate stack; 
   a second contact plug, with the second vertical plane being between the second contact plug and the second gate stack; and   a second silicide layer underlying the second contact plug and in the p-type source/drain region, wherein the second silicide layer comprises a third concave top surface.   
     
     
         19 . The device of  claim 18 , wherein the first silicide layer penetrates through a first capping layer of the n-type source/drain region, and the second silicide layer penetrates through a second capping layer of the p-type source/drain region. 
     
     
         20 . The device of  claim 18 , wherein the first silicide layer and the second silicide layer are in contact with a first middle layer of the n-type source/drain region and a second middle layer of the p-type source/drain region, respectively, and the first middle layer and the second middle layer are in contact with the first capping layer and the second capping layer, respectively.