Embedded stressors in epitaxy source/drain regions

Abstract

A method includes forming a semiconductor fin, forming a gate stack on the semiconductor fin, and a gate spacer on a sidewall of the gate stack. The method further includes recessing the semiconductor fin to form a recess, performing a first epitaxy process to grow a first epitaxy semiconductor layer in the recess, wherein the first epitaxy semiconductor layer, and performing a second epitaxy process to grow an embedded stressor extending into the recess. The embedded stressor has a top portion higher than a top surface of the semiconductor fin, with the top portion having a first sidewall contacting a second sidewall of the gate spacer, and with the sidewall having a bottom end level with the top surface of the semiconductor fin. The embedded spacer has a bottom portion lower than the top surface of the semiconductor fin.

What is claimed is: 
     
         1 . A device comprising:
 a semiconductor fin;   a gate stack on the semiconductor fin;   a gate spacer on a sidewall of the gate stack; and   a source/drain region aside of the gate spacer and comprising:
 a first semiconductor layer contacting a sidewall of the semiconductor fin, wherein the first semiconductor layer has a first phosphorous concentration; 
 a second semiconductor layer over and contacting the first semiconductor layer, wherein a first topmost tip of a first top portion of the second semiconductor layer is joined to a top corner of the semiconductor fin, and one of a top surface and a bottom surface of the first top portion has a ( 111 ) lattice plane, and the second semiconductor layer has a second phosphorous concentration higher than the first phosphorous concentration; and 
 an embedded stressor over and contacting the second semiconductor layer, wherein the embedded stressor has a third phosphorous concentration higher than the second phosphorous concentration, and the embedded stressor comprises:
 an upper portion contacting the gate spacer to form a vertical interface; and 
 a lower portion lower than the top corner of the semiconductor fin. 
 
   
     
     
         2 . The device of  claim 1 , wherein the first semiconductor layer further comprises a second top portion with a second topmost tip joined to the first topmost tip and the top corner of the semiconductor fin. 
     
     
         3 . The device of  claim 1 , wherein the top surface of the first top portion of the second semiconductor layer is on a ( 111 ) lattice plane. 
     
     
         4 . The device of  claim 1 , wherein the bottom surface of the first top portion of the second semiconductor layer is on a ( 111 ) lattice plane. 
     
     
         5 . The device of  claim 1  further comprising a third epitaxy layer over and contacting the embedded stressor, wherein the third epitaxy layer has a fourth phosphorous concentration lower than the third phosphorous concentration. 
     
     
         6 . The device of  claim 5 , wherein the third epitaxy layer comprises germanium in addition to silicon and phosphorous. 
     
     
         7 . The device of  claim 5  further comprising a silicide layer and a contact plug over and contacting the silicide layer, wherein the silicide layer and the contact plug collectively penetrate through the third epitaxy layer, and the silicide layer is over and contacting the embedded stressor. 
     
     
         8 . The device of  claim 1 , wherein the second semiconductor layer further comprises a curved top surface and a curved bottom surface connecting to the top surface and the bottom surface, respectively, of the first top portion of the second semiconductor layer. 
     
     
         9 . A device comprising:
 a semiconductor substrate;   isolation regions extending into the semiconductor substrate;   a semiconductor fin protruding higher than top surfaces of the isolation regions;   a gate stack on a top surface and sidewalls of the semiconductor fin; and   a source/drain region on a side of the semiconductor fin, wherein the source/drain region comprises:
 a first semiconductor layer having a first dopant concentration; and 
 an embedded stressor over and contacting the first semiconductor layer, wherein the embedded stressor has a second dopant concentration higher than the first dopant concentration, and wherein the embedded stressor has an upper portion higher than the top surface of the semiconductor fin, and a lower portion lower than the top surface of the semiconductor fin. 
   
     
     
         10 . The device of  claim 9  further comprising a gate spacer on a sidewall of the gate stack, wherein the upper portion of the embedded stressor contacts the gate spacer to form a vertical interface, and wherein a bottom surface of the embedded stressor is slanted, and joins to a point where a bottom of an outer surface of the gate spacer joins a top end of a sidewall of the semiconductor fin. 
     
     
         11 . The device of  claim 9 , wherein the embedded stressor has a V-shaped bottom surface. 
     
     
         12 . The device of  claim 9  further comprising a source/drain silicide region over and contacting the embedded stressor, wherein the source/drain silicide region has a V-shape in a cross-sectional view. 
     
     
         13 . The device of  claim 9 , wherein the embedded stressor comprises silicon phosphorous, and the device further comprises a capping layer over the embedded stressor, and wherein the capping layer comprises silicon, germanium, and phosphorous. 
     
     
         14 . The device of  claim 9  further comprising a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer has a lower dopant concentration than the first semiconductor layer. 
     
     
         15 . The device of  claim 14 , wherein the first semiconductor layer has a first facet having a first top end, the second semiconductor layer has a second facet having a second top end, and wherein the first top end joins the second top end, and further joins a top corner of the semiconductor fin. 
     
     
         16 . The device of  claim 15 , wherein one of the first facet and one of the second facet is on a ( 111 ) surface plane of the source/drain region. 
     
     
         17 . The device of  claim 9 , wherein the embedded stressor comprises a V-shaped bottom surface, with a topmost point of the V-shaped bottom surface being at a same level as the top surface of the semiconductor fin. 
     
     
         18 . A device comprising:
 a semiconductor fin;   a gate stack on the semiconductor fin; and   a source/drain region on a side of the semiconductor fin, wherein the source/drain region comprises an embedded stressor, and the embedded stressor comprises:
 a V-shaped bottom surface, wherein a top end of the V-shaped bottom surface is at a same level as a top surface of the semiconductor fin; and 
 a V-shaped top surface, wherein a first portion of the V-shaped top surface is higher than the top surface of the semiconductor fin, and a second portion of the V-shaped top surface is lower than the top surface of the semiconductor fin. 
   
     
     
         19 . The device of  claim 18  further comprising a semiconductor layer underlying the embedded stressor, wherein the semiconductor layer comprises a facet on a ( 111 ) surface plane of the semiconductor layer. 
     
     
         20 . The device of  claim 19 , wherein the facet on the ( 111 ) surface plane extends to join a top corner of the semiconductor fin.