Methods of charging local input/output lines of memory devices, and related devices and systems

Abstract

Methods of operating a memory device are disclosed. A method may include receiving a read command, performing a read operation in response to the read command, and receiving an additional command without precharging the local input/output line subsequent to performing the read operation and prior to receiving the additional command. Memory devices and systems are also disclosed.

What is claimed is: 
     
         1 . A method of operating a memory device, comprising:
 performing, responsive to a read command, a read operation via a local input/output (LIO) line of the memory device; and   receiving an additional command without precharging the LIO line after performing the read operation and prior to receiving the additional command.   
     
     
         2 . The method of  claim 1 , further comprising, responsive to the read command:
 disconnecting the LIO line from a digit line of the memory device, wherein the LIO line retains a charge based on a charge of the digit line for a duration of time following disconnection of the LIO line from the digit line; and   disconnecting a main input/output (MIO) line from the LIO line.   
     
     
         3 . The method of  claim 2 , further comprising, responsive to the read command, charging the LIO line with a charge between high and low after the duration of time. 
     
     
         4 . The method of  claim 2 , further comprising:
 responsive to the read command:
 setting an equalize-control signal low, wherein the memory device is configured to interpret the equalize-control signal as an indication of whether the LIO line is to be charged with a charge between high and low; and 
 setting the equalize-control signal high after the duration of time. 
   
     
     
         5 . The method of  claim 2 , further comprising:
 responsive to the read command:
 setting an equalize-control signal low, wherein the memory device is configured to interpret the equalize-control signal as an indication of whether the LIO line is to be charged with a charge between high and low; 
 setting a column-select signal high, wherein the memory device is configured to interpret the column-select signal as an indication of whether the LIO line is to be connected to the digit line; 
 setting a read-state signal high, wherein the memory device is configured to interpret the read-state signal as an indication of whether the MIO line is to be connected to the LIO line; 
 setting the column-select signal low; 
 setting the read-state signal low; and 
 setting the equalize-control signal high. 
   
     
     
         6 . The method of  claim 1 , wherein receiving the additional command without precharging the LIO line comprises receiving the additional command without performing an LIO precharge operation after performing the read operation and prior to receiving the additional command. 
     
     
         7 . A memory device, comprising:
 a local input/output (LIO) line; and   circuitry configured to:
 perform, via the LIO line, a read operation responsive to a read command; and 
 receive an additional command without precharging the LIO line after performance of the read operation and prior to receipt of the additional command. 
   
     
     
         8 . The memory device of  claim 7 , wherein the circuitry is such that during a duration of time after the performance of the read operation and prior to the receipt of the additional command, the LIO line retains a charge based on a charge of a digit line, the digit line coupled to a memory cell of the memory device. 
     
     
         9 . The memory device of  claim 7 , wherein the circuitry is further configured to, responsive to the read command:
 disconnect the LIO line from a digit line of the memory device, wherein the LIO line retains a charge based on a charge of the digit line for a duration of time following disconnection of the LIO line from the digit line; and   disconnect a main input/output (MIO) line from the LIO line.   
     
     
         10 . The memory device of  claim 9 , wherein the circuitry is further configured to, responsive to the read command, charge the LIO line with a charge between high and low following the duration of time. 
     
     
         11 . The memory device of  claim 9 , wherein the circuitry is further configured to, responsive to the read command:
 set an equalize-control signal low, wherein the memory device is configured to interpret the equalize-control signal as an indication of whether the LIO line is to be charged with a charge between high and low; and   set the equalize-control signal high after the duration of time.   
     
     
         12 . The memory device of  claim 9 , wherein the circuitry is further configured to, responsive to the read command:
 set an equalize-control signal low, wherein the memory device is configured to interpret the equalize-control signal as an indication of whether the LIO line is to be charged with a charge between high and low;   set a column-select signal high, wherein the memory device is configured to interpret the column-select signal as an indication of whether the LIO line is to be connected to the digit line;   set a read-state signal high, wherein the memory device is configured to interpret the read-state signal as an indication of whether the MIO line is to be connected to the LIO line;   set the column-select signal low;   set the read-state signal low; and   set the equalize-control signal high.   
     
     
         13 . The memory device of  claim 9 , wherein the circuitry is further configured to, responsive to the read command:
 charge a word line; and   discharge the word line.   
     
     
         14 . A system, comprising:
 at least one input device;   at least one output device;   at least one processor device operably coupled to the input device and the output device; and   at least one memory device operably coupled to the at least one processor device and comprising:
 circuitry configured to:
 perform, via a local input/output (LIO) line, a read operation responsive to a read command; and 
 receive an additional command without precharging the LIO line after performance of the read operation and prior to receipt of the additional command. 
 
   
     
     
         15 . The system of  claim 14 , wherein the circuitry is such that during a duration of time after the performance of the read operation and prior to the receipt of the additional command, the LIO line retains a charge based on a charge of a digit line, the digit line coupled to a memory cell of the memory device. 
     
     
         16 . The system of  claim 14 , wherein the circuitry is further configured to, responsive to the read command:
 disconnect the LIO line from a digit line wherein the LIO line retains a charge based on a charge of the digit line for a duration of time following disconnection of the LIO line from the digit line; and   disconnect a main input/output (MIO) line from the LIO line.   
     
     
         17 . The system of  claim 16 , wherein the circuitry is further configured to, responsive to the read command, charge the LIO line with a charge between high and low following the duration of time. 
     
     
         18 . The system of  claim 16 , wherein the circuitry is further configured to, responsive to the read command:
 set an equalize-control signal low, wherein the memory device is configured to interpret the equalize-control signal as an indication of whether the LIO line is to be charged with a charge between high and low; and   set the equalize-control signal high after the duration of time.   
     
     
         19 . The system of  claim 16 , wherein the circuitry is configured to receive the additional command without performing an LIO precharge operation after performing the read operation. 
     
     
         20 . The system of  claim 16 , wherein the circuitry is further configured to, responsive to the read command:
 charge a word line; and   discharge the word line after the word line is charged.