Memory controller for micro-threaded memory operations

Abstract

A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

1 . (canceled) 
     
     
         2 . A memory controller to control a memory device, wherein the memory device has bank groups, each bank group comprising banks of memory cells, the memory controller comprising:
 a command interface to transmit on a time-multiplexed bases, to the memory device, via at least one link that is to couple the command interface with the memory device,
 row activation commands to instruct row activations, and 
 column access commands to instruct column accesses; 
   wherein
 a first interval is to transpire between transmission by the command interface of back-to-back row activations to banks within different ones of the bank groups, 
 a second interval is to transpire between transmission by the command interface of back-to-back row activations to banks within a common one of the bank groups, 
 a third interval is to transpire between transmission by the command interface of back-to-back column accesses to banks within different ones of the bank groups, 
 a fourth interval is to transpire between transmission by the command interface of back-to-back column accesses to banks within a common one of the bank groups, 
 the first interval is shorter than the second interval, and 
 the third interval is shorter than the fourth interval. 
   
     
     
         3 . The memory controller of  claim 2 , wherein:
 the memory controller further comprises circuitry to transmit a clock signal to the memory device, the clock signal having clock transitions;   each of the first interval, the second interval, the third interval and the fourth interval are defined by respective numbers of the clock transitions; and   the third interval is shorter than the first interval.   
     
     
         4 . The memory controller of  claim 2 , wherein:
 each bank includes a first sub-bank and a second sub-bank, the first sub-bank is in a first bank group of the bank groups, and the second sub-bank is in a second bank group of the bank groups; and   the command interface is to transmit two column access commands for a given row activation command, wherein the given row activation command is to cause the memory device to access a corresponding row in each of the first sub-bank and the second sub-bank, and wherein the two column access commands are to cause the memory device to access respectively-addressed columns in the first sub-bank and the second-sub-bank.   
     
     
         5 . The memory controller of  claim 2 , wherein:
 each bank includes a first sub-bank and a second sub-bank, the first sub-bank is in a first bank group of the bank groups, and the second sub-bank is in a second bank group of the bank groups; and   the command interface is to transmit two column access commands for a given row activation command, wherein the given row activation command is to cause the memory device to access a corresponding row in a selected one of the first sub-bank and the second sub-bank, and wherein the two column access commands are to cause the memory device to access respectively-addressed columns in the selected one of the first sub-bank and the second-sub-bank.   
     
     
         6 . The memory controller of  claim 2 , further comprising circuitry to queue the row activation commands and the column activation commands, wherein the circuitry to queue is to queue at least one column access command for each row activation command, in order to access a column within a row activated by a corresponding row activation command, and wherein the command interface is to transmit bank address information from the memory controller to the memory device for each row activation command and for each column access command, in order to select a bank and in order to select one of the bank groups. 
     
     
         7 . The memory controller of  claim 6 , wherein the circuitry to queue the row activation commands and the column activation commands is to queue, for a given row activation command, at least two column access commands, in order to access different columns within a row activated by the given row activation command. 
     
     
         8 . The memory controller of  claim 2 , wherein the memory controller further comprises a data interface to transfer data with the memory device via links, using respective, mutually-exclusive subsets of the links to transfer data in association with the back-to-back column accesses to banks within different ones of the bank groups. 
     
     
         9 . The memory controller of  claim 2 , wherein:
 the memory controller further comprises a data interface to transfer data with the memory device via links, in association with each column access command; and   the memory controller further comprises serialization/deserialization circuitry to transfer serialized data with the memory device over each of the links used to transfer data in association with each column access command.   
     
     
         10 . The memory controller of  claim 2 , wherein the memory controller further comprises a data interface to transfer each of data and write mask values with the memory device, via respective link subsets. 
     
     
         11 . The memory controller of  claim 2 , wherein the memory controller is to transmit interleaved row activation commands and interleaved column access commands for back-to-back data accesses in different ones of the bank groups, and is to transmit bank address information as part of each command of the row activation commands and column access commands, to select a bank group of the bank groups, and to select a bank within the selected bank group. 
     
     
         12 . The memory controller of  claim 2 , wherein the first interval is longer than the third interval and the second interval is longer than the fourth interval. 
     
     
         13 . A memory controller to control a memory device, wherein the memory device has bank groups, each bank group comprising banks of memory cells, the memory controller comprising:
 circuitry to transmit a clock signal to the memory device, the clock signal having clock transitions;   a command interface to transmit on a time-multiplexed bases, to the memory device, via at least one link that is to couple the command interface with the memory device,
 row activation commands to instruct row activations, and 
 column access commands to instruct column accesses; 
   a data interface to transfer data with the memory device in association with each column access command;   wherein
 a first interval, defined by a first number of clock transitions, is to transpire between transmission by the command interface of back-to-back row activations to banks within different ones of the bank groups, 
 a second interval, defined by a second number of clock transitions, is to transpire between transmission by the command interface of back-to-back row activations to banks within a common one of the bank groups, 
 a third interval, defined by a third number of clock transitions, is to transpire between transmission by the command interface of back-to-back column accesses to banks within different ones of the bank groups, 
 a fourth interval, defined by a fourth number of clock transitions, is to transpire between transmission by the command interface of back-to-back column accesses to banks within a common one of the bank groups, 
 the first interval is shorter than the second interval, and 
 the third interval is shorter than the fourth interval. 
   
     
     
         14 . The memory controller of  claim 13 , wherein:
 each bank includes a first sub-bank and a second sub-bank, the first sub-bank is in a first bank group of the bank groups, and the second sub-bank is in a second bank group of the bank groups; and   the command interface is to transmit two column access commands for a given row activation command, wherein the given row activation command is to cause the memory device to access a corresponding row in each of the first sub-bank and the second sub-bank, and wherein the two column access commands are to cause the memory device to access respectively-addressed columns in the first sub-bank and the second-sub-bank.   
     
     
         15 . The memory controller of  claim 13 , wherein:
 each bank includes a first sub-bank and a second sub-bank, the first sub-bank is in a first bank group of the bank groups, and the second sub-bank is in a second bank group of the bank groups; and   the command interface is to transmit two column access commands for a given row activation command, wherein the given row activation command is to cause the memory device to access a corresponding row in a selected one of the first sub-bank and the second sub-bank, and wherein the two column access commands are to cause the memory device to access respectively-addressed columns in the selected one of the first sub-bank and the second-sub-bank.   
     
     
         16 . The memory controller of  claim 13 , further comprising circuitry to queue the row activation commands and the column activation commands, wherein the circuitry to queue is to queue at least one column access command for each row activation command, in order to access a column within a row activated by a corresponding row activation command, and wherein the command interface is to transmit bank address information from the memory controller to the memory device for each row activation command and for each column access command, in order to select a bank and in order to select one of the bank groups. 
     
     
         17 . The memory controller of  claim 16 , wherein the circuitry to queue the row activation commands and the column activation commands is to queue, for a given row activation command, at least two column access commands, in order to access different columns within a row activated by the given row activation command. 
     
     
         18 . The memory controller of  claim 13 , wherein the data interface is to transfer data with the memory device using respective, mutually-exclusive subsets of the links to transfer data in association with the back-to-back column accesses to banks within different ones of the bank groups. 
     
     
         19 . The memory controller of  claim 13 , wherein the memory controller further comprises serialization/deserialization circuitry to transfer serialized data with the memory device over each of the links used to transfer data in association with each column access command. 
     
     
         20 . A method of operation in a memory controller of controlling a memory device, the memory device having bank groups, each bank group having banks of memory, the method comprising:
 transmitting a clock signal to the memory device from the memory controller, the clock signal having clock transitions;   transmitting to the memory device from the memory controller, via a command interface having at least one link, row activation commands to instruct respective row activations and column access commands to instruct respective column accesses, each row activation command to specify a respective one of the bank groups for the row activations, and each column access command to specify a respective one of the bank groups for each column access, such that
 a first interval, defined by a first number of clock transitions to transpire between back-to-back row activations to banks within different ones of the bank groups, is shorter than a second interval, defined by a second number of clock transitions to transpire between back-to-back row activations to banks within a common one of the bank groups, and 
 a third interval, defined by a third number of clock transitions to transpire between back-to-back column accesses to banks within different ones of the bank groups, is shorter than a fourth interval, defined by a fourth number of clock transitions to transpire between back-to-back column accesses to banks within a common one of the bank groups; and 
   wherein each of the row activation commands and the column access commands are to be received via the at least one link, on a time-multiplexed basis.   
     
     
         21 . The method of  claim 20 , wherein:
 each bank includes a first sub-bank and a second sub-bank;   the first sub-bank is in a first bank group of the bank groups;   the second sub-bank is in a second bank group of the bank groups;   the method further comprises transmitting two column access commands for a given row activation command, wherein the given row activation command is to cause the memory device to access a corresponding row in each of the first sub-bank and the second sub-bank, and wherein the two column access commands are to cause the memory device to access respectively-addressed columns in the first sub-bank and the second-sub-bank.   
     
     
         22 . The method of  claim 20 , wherein:
 the method further comprises transmitting bank address information as part of each command of the row activation commands and column access commands, to communicate memory controller selection of a bank group of the bank groups, and to communicate memory controller selection of a bank within the selected bank group; and   the third interval is shorter than the first interval.