System-on-chip having multiple circuits and memory controller in separate and independent power domains

Abstract

Examples of the present disclosure generally relate to integrated circuits, such as a system-on-chip (SoC), that include a memory subsystem. In some examples, an integrated circuit includes a first master circuit in a first power domain on a chip; a second master circuit in a second power domain on the chip; and a first memory controller in a third power domain on the chip. The first master circuit and the second master circuit each are configured to access memory via the first memory controller. The first power domain and the second power domain each are separate and independent from the third power domain.

1 - 9 . (canceled) 
     
     
         10 . A method of operating an integrated circuit, the method comprising:
 selectively entering a first master circuit and a second master circuit of a plurality of master circuits of the integrated circuit into one of a plurality of power modes; and   accessing memory by the first master circuit via a first memory controller of the integrated circuit independent of the selected one of the plurality of power modes of the second master circuit, wherein the first memory controller is in a power domain separate from a power domain of the second master circuit.   
     
     
         11 . The method of  claim 10 , wherein the first memory controller is not included in a master circuit. 
     
     
         12 . The method of  claim 10 , wherein accessing the memory by the first master circuit via the first memory controller comprises communicating between the first master circuit and the first memory controller via a configurable interconnect network of the integrated circuit. 
     
     
         13 . The method of  claim 12 , wherein the configurable interconnect network is in a power domain separate from the power domain of the first master circuit, the power domain of the second master circuit, and the first memory controller. 
     
     
         14 . The method of  claim 12  further:
 comprising accessing the memory by the first master circuit via a second memory controller of the integrated circuit and the configurable interconnect network, wherein the second memory controller is in a power domain separate from the power domain of the first master circuit. 
 
     
     
         15 . The method of  claim 14 , wherein the power domain of the second memory controller differs from the power domain of the first memory controller. 
     
     
         16 . The method of  claim 15 , wherein the power domain of the second master circuit differs from the power domain of the second memory controller. 
     
     
         17 . The method of  claim 12 , wherein communicating between the first master circuit and the first memory controller via the configurable interconnect network includes communicating between the first master circuit and the first memory controller via at least one of a plurality of virtual channels of a physical channel of the configurable interconnect network. 
     
     
         18 . The method of  claim 10 , wherein the selected one of the plurality of power modes of the first master circuit differs from the selected one of the plurality of power modes of the second master circuit. 
     
     
         19 . An integrated circuit comprising:
 a plurality of master circuits, a first master circuit and a second master circuit of the plurality of master circuits configured to selectively enter into one of a plurality of power modes; and   a first memory controller, wherein the first master circuit is configured to access a memory via the first memory controller independent of the selected one of the plurality of power modes of the second master circuit, wherein the first memory controller is in a power domain separate from a power domain of the second master circuit.   
     
     
         20 . The integrated circuit of  claim 19 , wherein the first memory controller is not included in a master circuit. 
     
     
         21 . The integrated circuit of  claim 19  further comprising a configurable interconnect network, wherein accessing the memory by the first master circuit via the first memory controller comprises communicating between the first master circuit and the first memory controller via the configurable interconnect network. 
     
     
         22 . The integrated circuit of  claim 21 , wherein the configurable interconnect network is in a power domain separate from each of the power domain of the first master circuit, the power domain of the second master circuit, and the power domain of the first memory controller. 
     
     
         23 . The integrated circuit of  claim 21  further comprising:
 a second memory controller, wherein the first master circuit is configured to access the memory via the second memory controller of the integrated circuit and the configurable interconnect network, wherein the second memory controller is in a power domain separate from the power domain of the first master circuit. 
 
     
     
         24 . The integrated circuit of  claim 23 , wherein the power domain of the second memory controller differs from the power domain of the first memory controller. 
     
     
         25 . The integrated circuit of  claim 23 , wherein the second memory controller is in a power domain separate from the power domain of the second master circuit. 
     
     
         26 . The integrated circuit of  claim 21 , wherein communicating between the first master circuit and the first memory controller via the configurable interconnect network includes communicating between the first master circuit and the first memory controller via at least one of a plurality of virtual channels of a physical channel of the configurable interconnect network. 
     
     
         27 . The integrated circuit of  claim 19 , wherein the selected one of the plurality of power modes of the first master circuit differs from the selected one of the plurality of power modes of the second master circuit. 
     
     
         28 . A method of operating an integrated circuit, the method comprising:
 entering a first master circuit of a plurality of master circuits of the integrated circuit into a first power mode of a plurality of power modes;   entering a second master circuit of the plurality of master circuits into a second power mode of the plurality of power modes, wherein the first power mode differs from the second power mode; and   accessing memory by the first master circuit via a first memory controller of the integrated circuit independent of the second power mode of the second master circuit, wherein the second power mode of the second master circuit is unaffected by accessing the memory by the first master circuit via the first memory controller, and wherein the first memory controller is not included in a master circuit and is in a power domain separate from each respective power domain of the plurality of master circuits.   
     
     
         29 . The method of  claim 28 , wherein accessing the memory by the first master circuit via the first memory controller comprises communicating between the first master circuit and the first memory controller via a configurable interconnect network of the integrated circuit, and wherein the configurable interconnect network is in a power domain separate from each of the respective power domains of the plurality of master circuits and the first memory controller.