Magnetic tunnel junction memory cell with a buffer-layer and methods for forming the same

Abstract

A memory cell structure including a dielectric cap layer disposed over a substrate and a first dielectric layer disposed over the dielectric cap layer. The memory cell structure may further include a buffer layer disposed over the first dielectric layer, a connection via structure embedded in the buffer layer, the first dielectric layer, and the dielectric cap layer. The memory cell structure may further include may further include a bottom electrode disposed on the connection via structure and the buffer layer, and a magnetic tunnel junction (MTJ) memory cell including one or more MTJ layers disposed on the bottom electrode.

What is claimed is: 
     
         1 . A method of forming a memory device, the method comprising:
 forming a dielectric layer stack comprising a connection-via-level dielectric layer comprising a first dielectric oxide material and a buffer layer comprising a second dielectric oxide material;   forming a connection via structure through the dielectric layer stack;   forming a bottom electrode layer and magnetic tunnel junction (MTJ) layers over the dielectric layer stack;   forming a metallic etch mask portion over the MTJ layers; and   patterning the MTJ layers and the bottom electrode layer into a magnetic tunnel junction (MTJ) memory cell by performing an ion beam etch process, wherein the second dielectric oxide material and the first dielectric oxide material have material compositions such that:   a ratio of an etch rate of the second dielectric oxide material to an etch rate of a material of the bottom electrode layer under an ion beam etch condition employed in the ion beam etch process is in a range from 0.8 to 1.3; and   a ratio of an etch rate of the first dielectric oxide material to the etch rate of the material of the bottom electrode layer under the ion beam etch condition employed in the ion beam etch process is in a range from 2.2 to 2.9.   
     
     
         2 . The method of  claim 1 , wherein the first dielectric oxide material comprises undoped silicate glass or a doped silicate glass. 
     
     
         3 . The method of  claim 2 , wherein the second dielectric oxide material comprises aluminum oxide or titanium pentoxide. 
     
     
         4 . The method of  claim 1 , wherein the dielectric layer stack further comprises a dielectric capping layer that underlies the connection-via-level dielectric layer. 
     
     
         5 . The method of  claim 4 , wherein the dielectric capping layer comprises a material selected from silicon nitride and silicon carbide. 
     
     
         6 . The method of  claim 1 , further comprising:
 a semiconductor substrate underlying the dielectric layer stack; and   dielectric material layers embedding metal interconnect structures and located between the semiconductor substrate and the dielectric layer stack, wherein the dielectric layer stack is formed over a topmost surface of the dielectric material layers.   
     
     
         7 . The method of  claim 1 , wherein the bottom electrode layer comprises titanium nitride. 
     
     
         8 . The method of  claim 1 , wherein the buffer layer after the ion beam etch process comprise a recessed surface that is formed above a horizontal plane including a bottom surface of the remaining portion of the buffer layer. 
     
     
         9 . The method of  claim 1 , further comprising removing a first portion of the buffer layer from a logic region to expose a top surface of the connection-via-level dielectric layer without removing a second portion of the buffer layer from a memory array region that includes the MTJ memory cell. 
     
     
         10 . The method of  claim 9 , further comprising forming a memory level dielectric layer directly on the top surface of the contact-via-level dielectric layer and the second portion of the buffer layer. 
     
     
         11 . A method of forming a memory device, the method comprising:
 forming a first metal line structure in a dielectric material layer overlying a substrate;   forming a dielectric layer stack including, from bottom to top, a dielectric cap layer, a connection-via-level dielectric layer, and a buffer layer over the first metal line structure and the dielectric material layer and;   forming a connection via structure through the dielectric layer stack on a top surface of the first metal line structure;   forming a bottom electrode layer and magnetic tunnel junction (MTJ) layers over the dielectric layer stack;   forming a metallic etch mask portion over the MTJ layers in a memory array region; and   patterning the MTJ layers and the bottom electrode layer into a magnetic tunnel junction (MTJ) memory cell by performing an ion beam etch process;   forming a dielectric spacer laterally surrounding the MTJ memory cell; and   forming a memory-level dielectric layer comprising a dielectric material which around the dielectric spacer, wherein the dielectric material of the memory-level dielectric layer is formed directly on a recessed horizontal surface segment of a top surface of the buffer layer in the memory array region, and directly contacts a horizontal surface of the connection-via-level dielectric layer in a logic region that is laterally spaced from the memory array region.   
     
     
         12 . The method of  claim 11 , wherein the buffer layer comprises aluminum oxide (Al 2 O 3 ). 
     
     
         13 . The method of  claim 11 , wherein the buffer layer comprises tantalum pentoxide (Ta 2 O 5 ). 
     
     
         14 . The method of  claim 11 , further comprising planarizing the memory-level dielectric layer such that the top surface of the memory-level dielectric layer is formed in a horizonal plane including a top surface of the metallic etch mask portion. 
     
     
         15 . The method of  claim 14 , further comprising depositing and patterning at least one dielectric etch stop layer such that the at least one dielectric etch stop layer covers the metallic etch mask portion and does not cover an area within the logic region. 
     
     
         16 . The method of  claim 15 , further comprising:
 forming a via-level dielectric layer over the at least one dielectric etch stop layer; and   forming a contact via structure and a connection via structure through the via-level dielectric layer, wherein the contact via structure vertically extends through, and contacts, the at least one dielectric etch stop layer and contacts a top surface of the metallic etch mask portion, and wherein the connection via structure vertically extends through, and contacts, the dielectric layer stack and contacts one of the first metal line structures.   
     
     
         17 . A method of forming a memory device, the method comprising:
 forming metal line structures in a dielectric material layers overlying a substrate;   forming a dielectric layer stack including, from bottom to top, a dielectric cap layer, a connection-via-level dielectric layer, and a buffer layer over the dielectric material layers;   forming an array of connection via structures through the dielectric layer stack on a respective one of the metal line structures; and   forming a bottom electrode layer and magnetic tunnel junction (MTJ) layers over the dielectric layer stack;   forming an array of metallic etch mask portions over the MTJ layers in a memory array region; and   patterning the MTJ layers and the bottom electrode layer into an array of stacks of a bottom electrode and a magnetic tunnel junction (MTJ) memory cell by performing an ion beam etch process, wherein a recessed top surface of the buffer layer is formed between neighboring pairs of the bottom electrodes within the array of stacks;   forming an array of a dielectric spacer around the array of stacks;   removing a portion of the buffer layer in a logic region that is adjacent to the memory array region, whereby a top surface of the connection-via-level dielectric layer is physically exposed in the logic region; and   forming a memory-level dielectric layer comprising a dielectric material directly on the array of dielectric spacer, segments of the recessed top surface of the buffer layer in the memory array region, and on the physically exposed top surface of the connection-via-level dielectric layer.   
     
     
         18 . The method of  claim 17 , wherein:
 the connection-via-level dielectric layer comprises a first dielectric oxide material;   the buffer layer comprises a second dielectric oxide material;   the array of stacks is patterned by performing an ion bean etch process;   a ratio of an etch rate of the second dielectric oxide material to an etch rate of a material of the bottom electrode layer under an ion beam etch condition employed in the ion beam etch process is in a range from 0.8 to 1.3; and   a ratio of an etch rate of the first dielectric oxide material to the etch rate of the material of the bottom electrode layer under the ion beam etch condition employed in the ion beam etch process is in a range from 2.2 to 2.9.   
     
     
         19 . The method of  claim 18 , wherein:
 the first dielectric oxide material comprises undoped silicate glass or a doped silicate glass; and   the second dielectric oxide material comprises aluminum oxide or titanium pentoxide.   
     
     
         20 . The method of  claim 19 , wherein the dielectric capping layer comprises a material selected from silicon nitride and silicon carbide.