Memory device and method of manufacturing the same

Abstract

A memory device includes: a gate stack on a substrate, including insulation layers and gate electrodes alternately stacked in a vertical direction, and defining a through hole in the vertical direction; and a pillar structure in the through hole, the pillar structure including: a plurality of channel portions in the through hole to face the gate electrodes and having annular horizontal cross-sections; a plurality of conductive layers in the through hole to face the insulation layers, having annular horizontal cross-sections, and having inner walls protruding toward a center of the through hole with respect to inner walls of the channel portions; and a variable resistance material layer on the inner walls of the channel portions and the inner walls of the conductive layers, in the through hole, and a first portion of the variable resistance material layer overlaps the conductive layers in the vertical direction.

What is claimed is: 
     
         1 . A memory device comprising:
 a gate stack on a substrate, the gate stack comprising a plurality of insulation layers and a plurality of gate electrodes alternately stacked in a vertical direction, and defining a through hole in the vertical direction; and   a pillar structure in the through hole,   wherein the pillar structure includes,
 a plurality of channel portions in the through hole to face the gate electrodes and having annular horizontal cross-sections, 
 a plurality of conductive layers in the through hole to face the insulation layers, having annular horizontal cross-sections, and having inner walls protruding toward a center of the through hole with respect to inner walls of the channel portions, and 
 a variable resistance material layer in the through hole on the inner walls of the channel portions and the inner walls of the conductive layers, wherein 
   a first portion of the variable resistance material layer overlaps the conductive layers in the vertical direction.   
     
     
         2 . The memory device of  claim 1 , wherein
 the inner wall of the channel portion and top surfaces of and bottom surfaces of the conductive layers define a plurality of recesses, and   the first portion of the variable resistance material layer is in the plurality of recesses.   
     
     
         3 . The memory device of  claim 2 , wherein in the plurality of recesses the first portion of the variable resistance material layer contacts the top surfaces of and the bottom surfaces of the conductive layers and the inner walls of the channel portions. 
     
     
         4 . The memory device of  claim 1 , wherein
 the gate stack further comprises a gate insulation layer covering top surfaces of and bottom surfaces of the gate electrodes, and   the gate insulation layer is between each of the gate electrodes and each of the corresponding channel portions.   
     
     
         5 . The memory device of  claim 1 , wherein
 the pillar structure further comprises spacers between the insulation layers and the conductive layers, and   top surfaces of and/or bottom surfaces of the spacers contact the channel portions.   
     
     
         6 . A memory device comprising:
 a gate stack on a substrate, comprising a plurality of insulation layers and a plurality of gate electrodes that are alternately stacked in a vertical direction, and defining a through hole in the vertical direction;   a plurality of channel portions in the through hole to face the gate electrodes;   a plurality of conductive layers in the through hole to face the insulation layers; and   a variable resistance material layer on first sidewalls of the channel portions and second sidewalls of the conductive layers, the variable resistance material layer in the through hole, and extending in the vertical direction.   
     
     
         7 . The memory device of  claim 6 , wherein each of the channel portions has an annular horizontal cross-sectional shape, and the channel portions are spaced apart from one another in the vertical direction. 
     
     
         8 . The memory device of  claim 6 , wherein
 the second sidewalls of the conductive layers protrude from the first sidewalls of the channel portions toward the inside of the through hole,   the sidewall of the channel portion and top surfaces and bottom surfaces of the conductive layers define a plurality of recesses, and   a first portion of the variable resistance material layer is in at least one of the plurality of recesses.   
     
     
         9 . The memory device of  claim 8 , wherein the variable resistance material layer contacts the top surfaces of and the bottom surfaces of the conductive layers and the first sidewalls of the channel portions, in the at least one of the plurality of recesses. 
     
     
         10 . The memory device of  claim 8 , wherein the first portion of the variable resistance material layer overlaps portions of the conductive layers in the vertical direction. 
     
     
         11 . The memory device of  claim 8 , further comprising:
 spacers between the insulation layers and the conductive layers,   wherein at least one of top surfaces or bottom surfaces of the spacers contact the channel portions.   
     
     
         12 . The memory device of  claim 6 , wherein
 the second sidewalls of the conductive layers align with the first sidewalls of the channel portions, and   the variable resistance material layer has vertically extending sidewalls.   
     
     
         13 . The memory device of  claim 12 , wherein the conductive layers overlap the channel portions in the vertical direction. 
     
     
         14 . The memory device of  claim 6 , wherein
 the gate stack further comprises a gate insulation layer covering top surfaces of and bottom surfaces of the gate electrodes, and   the gate insulation layer is between each of the gate electrodes and each of the corresponding channel portions.   
     
     
         15 . The memory device of  claim 6 , wherein
 the through hole comprises an extended space extending in lateral directions toward the gate electrodes,   the conductive layers extend from third sidewalls of the corresponding insulation layers onto top surfaces of and bottom surfaces of the insulation layers inside the extended space, respectively, and   a first portion of the variable resistance material layer is in the extended space.   
     
     
         16 . The memory device of  claim 15 , wherein the variable resistance material layer contacts the top surfaces of and the bottom surfaces of the conductive layers, in the extended space. 
     
     
         17 . The memory device of  claim 16 , wherein the first portion of the variable resistance material layer, portions of the conductive layers, and portions of the insulation layers overlap one another in the vertical direction. 
     
     
         18 . The memory device of  claim 15 , wherein
 the gate stack further comprises a gate insulation layer between the gate electrodes and the channel portions, and   the gate insulation layer is not between the gate electrodes and the insulation layers.   
     
     
         19 . A memory device comprising:
 a gate stack on a substrate, comprising a plurality of insulation layers and a plurality of gate electrodes alternately stacked in a vertical direction, and defining a through hole extending in the vertical direction;   a pillar structure in the through hole and comprising,
 a plurality of channel portions in the through hole to face the gate electrodes, 
 a plurality of conductive layers in the through hole, in the vertical direction alternately with the channel portions, and comprising at least one of a metal or a metal nitride, and 
 a variable resistance material layer on inner walls of the channel portions and inner walls of the conductive layers, in the through hole; 
   the memory device further comprising a bit line plug on a top surface of the pillar structure; and   a bit line disposed on the bit line plug.   
     
     
         20 . The memory device of  claim 19 , wherein
 the inner wall of the channel portion and top surfaces and bottom surfaces of the conductive layers define a plurality of recesses, and   a first portion of the variable resistance material layer is in the plurality of recesses.