Fin field-effect transistor and method of forming the same

Abstract

A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes a gate spacer over the semiconductor fin. A lower portion of the gate spacer surrounds a first region and an upper portion of the gate spacer surrounds a second region. The semiconductor device includes a gate dielectric within the first region. The semiconductor device includes a metal gate within the first region. The semiconductor device includes a dielectric protection layer, in contact with the gate dielectric layer, that includes a first portion within the second region and a second portion lining a top surface of the metal gate.

What is claimed is: 
     
         1 . A method of forming a semiconductor device, comprising:
 forming a gate trench over a semiconductor fin, the gate trench being lined with gate spacers;   forming a gate structure within a lower portion of the gate trench to expose the gate spacers in an upper portion of the gate trench;   depositing a blanket dielectric layer in the upper portion of the gate trench;   depositing a polymer layer over the blanket dielectric layer to completely fill the upper portion of the gate trench;   etching the polymer layer to partially expose the blanket dielectric layer in the gate trench;   removing the exposed blanket dielectric layer to partially expose the gate spacers; and   removing a remaining portion of the polymer layer to expose the blanket dielectric layer, wherein the gate spacers vertically extend above the blanket dielectric layer.   
     
     
         2 . The method of  claim 1 , wherein forming the gate structure includes forming a metal gate over a gate dielectric layer, and wherein sidewalls of the blanket dielectric layer extend vertically from sidewalls of the gate dielectric layer. 
     
     
         3 . The method of  claim 2 , wherein the blanket dielectric layer directly contacts top surfaces of the metal gate and the gate dielectric layer. 
     
     
         4 . The method of  claim 2 , wherein the gate dielectric layer includes a high-k dielectric material, and the blanket dielectric layer includes the same high-k dielectric material as the gate dielectric layer. 
     
     
         5 . The method of  claim 1 , wherein removing the exposed blanket dielectric layer includes performing an isotropic etching process. 
     
     
         6 . The method of  claim 1 , wherein etching the polymer layer includes performing an ashing process. 
     
     
         7 . The method of  claim 1 , wherein the blanket dielectric layer includes at least one material selected from the group consisting of a metal oxide or a metal silicate, the metal oxide or the metal silicate including at least one element selected from the group consisting of Hf, Al, Zr, La, Mg, Ba, Ti, or Pb. 
     
     
         8 . The method of  claim 1 , wherein the blanket dielectric layer includes at least one material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride. 
     
     
         9 . The method of  claim 1 , wherein removing the exposed blanket dielectric layer results in a top surface of the blanket dielectric layer to be coplanar with a top surface of the etched polymer layer. 
     
     
         10 . A method of forming a semiconductor device, comprising:
 forming a gate trench over a semiconductor fin, the gate trench being lined with gate spacers;   forming a gate structure within a lower portion of the gate trench to expose the gate spacers in an upper portion of the gate trench;   conformally depositing a first dielectric layer in the upper portion of the gate trench;   forming a sacrificial layer over the first dielectric layer to fill the gate trench;   etching the sacrificial layer to expose portions of the first dielectric layer in the gate trench;   removing the exposed portions of the first dielectric layer to expose the gate spacers;   removing a remaining portion of the sacrificial layer such that the gate spacers protrude from a remaining portion of the first dielectric layer;   forming a second dielectric layer over the remaining portion of the first dielectric layer; and   planarizing the second dielectric layer such that the gate spacers, the remaining portion of the first dielectric layer, and the second dielectric layer are coplanar.   
     
     
         11 . The method of  claim 10 , wherein forming the gate structure includes forming a metal gate over a gate dielectric layer, and wherein sidewalls of the first dielectric layer and sidewalls of the gate dielectric layer both directly contact the gate spacers. 
     
     
         12 . The method of  claim 11 , wherein the gate dielectric layer includes a high-k dielectric material, and the first dielectric layer includes the same high-k dielectric material as the gate dielectric layer. 
     
     
         13 . The method of  claim 12 , wherein the high-k dielectric material includes at least one material selected from the group consisting of a metal oxide or a metal silicate. 
     
     
         14 . The method of  claim 10 , wherein the first dielectric layer and the second dielectric layer have different compositions. 
     
     
         15 . The method of  claim 10 , wherein planarizing the second dielectric layer removes portions of the second dielectric layer and the gate spacers. 
     
     
         16 . The method of  claim 10 , further comprising forming a gate contact extending through the second dielectric layer and the remaining portion of the first dielectric layer. 
     
     
         17 . A method of forming a semiconductor device, comprising:
 forming a pair of source/drain regions separated by a channel region in a semiconductor fin,   forming a gate trench over the channel region and surrounded by gate spacers;   forming a gate structure within a lower portion of the gate trench;   depositing a first dielectric layer over the gate structure in an upper portion of the gate trench, wherein sidewalls of the first dielectric layer are vertically connected with sidewalls of the gate structure;   forming a sacrificial layer over the first dielectric layer to fill the gate trench;   removing a portion of the sacrificial layer to expose the first dielectric layer;   removing the exposed first dielectric layer such that a remaining portion of the first dielectric layer is coplanar with a remaining portion of the sacrificial layer;   removing the remaining portion of the sacrificial layer to expose the remaining portion of the first dielectric layer;   depositing a second dielectric layer over the remaining portion of the first dielectric layer; and   planarizing the second dielectric layer to shorten the gate spacers.   
     
     
         18 . The method of  claim 17 , further comprising:
 forming a pair of source/drain contacts each electrically connected to a corresponding one of the pair of source/drain regions; and   forming a gate contact electrically connected to the gate structure, wherein the gate contact extends through the second dielectric layer and the first dielectric layer.   
     
     
         19 . The method of  claim 18 , wherein the gate contact is electrically isolated from any of the pair of source/drain contacts by at least a portion of the first dielectric layer. 
     
     
         20 . The method of  claim 17 , wherein forming the gate structure includes forming a metal gate over a gate dielectric layer, wherein the gate dielectric layer and the first dielectric layer have the same composition, and wherein the first dielectric layer and the second dielectric layer have different compositions.