Gate trench power semiconductor devices having improved deep shield connection patterns
Abstract
A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type and a well region of a second conductivity type, a plurality of gate trenches including respective gate insulating layers and gate electrodes therein extending into the drift region, respective shielding patterns of the second conductivity type in respective portions of the drift region adjacent the gate trenches, and respective conduction enhancing regions of the first conductivity type in the respective portions of the drift region. The drift region comprises a first concentration of dopants of the first conductivity type, and the respective conduction enhancing regions comprise a second concentration of the dopants of the first conductivity type that is higher than the first concentration. Related devices and fabrication methods are also discussed.
Claims
exact text as granted — not AI-modifiedThat which is claimed:
1 . A power semiconductor device, comprising:
a semiconductor layer structure comprising a drift region of a first conductivity type and a well region of a second conductivity type; and a plurality of gate trenches extending into the drift region, wherein the gate trenches are spaced apart from one another in a first direction, and wherein respective portions of the drift region adjacent the gate trenches comprise a concentration of dopants of the first conductivity type that varies along the first direction.
2 . The power semiconductor device of claim 1 , wherein the drift region comprises respective conduction enhancing regions of the first conductivity type that are spaced apart from respective corners of the gate trenches along the first direction,
wherein the concentration of the dopants of the first conductivity type comprises a first concentration proximate the respective corners of the gate trenches and a second concentration in the respective conduction enhancing regions, wherein the second concentration is higher than the first concentration.
3 . The power semiconductor device of claim 2 , wherein the concentration of the dopants of the first conductivity type further comprises a concentration gradient of the dopants of the first conductivity type between the first concentration and the second concentration along the first direction.
4 . The power semiconductor device of claim 2 , wherein the second concentration is higher than the first concentration by a factor of about 2 or more.
5 . The power semiconductor device of claim 2 , further comprising:
respective shielding patterns of the second conductivity type in the respective portions of the drift region between the gate trenches and/or under the gate trenches, wherein the respective conduction enhancing regions are between the gate trenches and extend into the drift region beyond a lower boundary of the respective shielding patterns, and wherein the respective conduction enhancing regions are offset from the respective shielding patterns towards the gate trenches, and/or wherein the respective conduction enhancing regions extend along at least one of a side or a lower boundary of the respective shielding patterns.
6 . The power semiconductor device of claim 2 , wherein, responsive to a voltage applied to the power semiconductor device, the respective portions of the drift region between the gate trenches comprise an electric field distribution having a peak that is distal from the respective corners of the gate trenches in the first direction.
7 . The power semiconductor device of claim 6 , wherein the peak of the electric field distribution is greater than a strength of the electric field distribution proximate the respective corners of the gate trenches by a factor of about 10 or more.
8 . A power semiconductor device, comprising:
a semiconductor layer structure comprising a drift region of a first conductivity type and a well region of a second conductivity type; and a plurality of gate trenches extending into the drift region, wherein, responsive to a voltage applied to the power semiconductor device, respective portions of the drift region between the gate trenches comprise an electric field distribution having a peak that is distal from respective corners of the gate trenches.
9 . The power semiconductor device of claim 8 , wherein the gate trenches are spaced apart from one another in a first direction, and wherein the electric field distribution in the respective portions of the drift region between the gate trenches is asymmetric along the first direction.
10 . The power semiconductor device of claim 9 , wherein the peak of the electric field distribution is greater than a strength of the electric field distribution proximate the respective corners of the gate trenches by a factor of about 10 or more.
11 . The power semiconductor device of claim 9 , wherein the respective portions of the drift region between the gate trenches comprise a concentration of dopants of the first conductivity type that varies along the first direction between adjacent ones of the gate trenches.
12 . The power semiconductor device of claim 11 , further comprising:
respective conduction enhancing regions of the first conductivity type that are spaced apart from the respective corners of the gate trenches along the first direction, wherein the concentration of the dopants of the first conductivity type comprises a first concentration proximate the respective corners of the gate trenches and a second concentration in the respective conduction enhancing regions, wherein the second concentration is higher than the first concentration.
13 . The power semiconductor device of claim 12 , wherein the concentration of the dopants of the first conductivity type further comprises a concentration gradient of the dopants of the first conductivity type between the first concentration and the second concentration along the first direction.
14 . The power semiconductor device of claim 12 , wherein the second concentration is higher than the first concentration by a factor of about 10 or more.
15 . The power semiconductor device of claim 12 , wherein the respective conduction enhancing regions comprise the peak of the electric field distribution.
16 . A power semiconductor device, comprising:
a semiconductor layer structure comprising a drift region of a first conductivity type and a well region of a second conductivity type; a plurality of gate trenches extending into the drift region; and respective shielding patterns of the second conductivity type in respective first portions of the drift region adjacent the gate trenches, wherein the gate trenches are spaced apart from one another in a first direction, and wherein respective second portions of the drift region adjacent the gate trenches comprise a concentration of dopants of the first conductivity type that varies along the first direction.
17 . The power semiconductor device of claim 16 , wherein the drift region comprises respective conduction enhancing regions of the first conductivity type that are spaced apart from respective corners of the gate trenches along the first direction,
wherein the concentration of the dopants of the first conductivity type comprises a first concentration proximate the respective corners of the gate trenches and a second concentration in the respective conduction enhancing regions, wherein the second concentration is higher than the first concentration.
18 . The power semiconductor device of claim 17 , wherein the concentration of the dopants of the first conductivity type further comprises a concentration gradient of the dopants of the first conductivity type that varies between the first concentration and the second concentration along the first direction.
19 . The power semiconductor device of claim 17 , wherein the second concentration is higher than the first concentration by a factor of about 2 or more.
20 . The power semiconductor device of claim 17 , wherein the respective conduction enhancing regions extend around a periphery of the respective shielding patterns.
21 . The power semiconductor device of claim 17 , wherein the respective conduction enhancing regions are in direct contact with the respective shielding patterns.
22 . The power semiconductor device of claim 16 , wherein the respective shielding patterns extend along bottom portions of the gate trenches, and wherein the concentration of dopants of the first conductivity type varies along the first direction between adjacent ones of the gate trenches.
23 . A power semiconductor device, comprising:
a semiconductor layer structure comprising a drift region of a first conductivity type and a well region of a second conductivity type; and a plurality of gate trenches extending into the drift region; and respective shielding patterns of the second conductivity type in respective portions of the drift region adjacent the gate trenches, wherein, responsive to a voltage applied to the power semiconductor device, respective portions of the drift region between the gate trenches comprise an electric field distribution having a peak that is distal from respective corners of the gate trenches.
24 . The power semiconductor device of claim 23 , wherein the gate trenches are spaced apart from one another in a first direction, and wherein the electric field distribution in the respective portions of the drift region between the gate trenches is asymmetric along the first direction.
25 . The power semiconductor device of claim 23 , wherein the gate trenches are spaced apart from one another along a first direction, wherein the respective shielding patterns extend along bottom portions of the gate trenches, and wherein the concentration of dopants of the first conductivity type varies along the first direction between adjacent ones of the gate trenches.Join the waitlist — get patent alerts
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