US2023369448A1PendingUtilityA1
High electron mobility transistor and method for fabricating the same
Assignee: UNITED MICROELECTRONICS CORPPriority: Dec 6, 2019Filed: Jul 13, 2023Published: Nov 16, 2023
Est. expiryDec 6, 2039(~13.4 yrs left)· nominal 20-yr term from priority
Inventors:Bo ChenChe-Hung HuangChun-Ming ChangYi-Shan HsuChih-Tung YehShin-Chuan HuangWen-Jung LiaoChun-Liang Hou
H10D 62/8503H10D 30/4732H10D 30/015H10D 62/824H10D 62/343H10D 62/115H10D 30/475H10D 30/47H01L 29/66462H01L 29/7783H01L 29/2003
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Claims
Abstract
A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method for fabricating high electron mobility transistor (HEMT), comprising:
forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.
2 . The method of claim 1 , further comprising forming a buffer layer on the substrate before forming the first barrier layer.
3 . The method of claim 1 , further comprising:
forming a second barrier layer on the first barrier layer adjacent to the spacer; forming a gate electrode on the hard mask; and forming a source electrode and a drain electrode adjacent to two sides of the spacer.
4 . The method of claim 3 , wherein the hard mask comprises a conductive material.
5 . The method of claim 1 , further comprising:
forming a second barrier layer on the first barrier layer adjacent to the spacer; forming a gate electrode in the hard mask and on the p-type semiconductor layer; and forming a source electrode and a drain electrode adjacent to two sides of the spacer.
6 . The method of claim 5 , wherein the hard mask comprises a dielectric material.
7 . The method of claim 1 , wherein the first barrier layer comprise Al x Ga 1-x N.
8 . A method for fabricating high electron mobility transistor (HEMT), comprising:
forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; patterning the p-type semiconductor layer; and forming a spacer adjacent to the p-type semiconductor layer.
9 . The method of claim 8 , further comprising forming a buffer layer on the substrate before forming the first barrier layer.
10 . The method of claim 8 , further comprising:
forming a second barrier layer on the p-type semiconductor layer and the first barrier layer adjacent to the spacer; forming a hard mask on the second barrier layer; planarizing the hard mask; forming a gate electrode on the p-type semiconductor layer; and forming a source electrode and a drain electrode adjacent to two sides of the spacer.
11 . The method of claim 10 , further comprising planarizing the hard mask and the second barrier layer so that top surfaces of the hard mask and the p-type semiconductor layer are coplanar.
12 . The method of claim 8 , wherein the first barrier layer comprise Al x Ga 1-x N.Join the waitlist — get patent alerts
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