In-situ thermal annealing of electrode to form seed layer for improving feram performance

Abstract

In some embodiments, the present disclosure relates to an integrated circuit (IC). The IC includes a substrate and an electrode disposed over the substrate. A ferroelectric layer is vertically stacked with the electrode. A seed layer that includes oxygen is vertically stacked between the electrode and the ferroelectric layer. The ferroelectric layer has a substantially uniform orthorhombic crystalline phase.

What is claimed is: 
     
         1 . An integrated circuit (IC), comprising:
 a substrate;   an electrode disposed over the substrate;   a ferroelectric layer vertically stacked with the electrode; and   a seed layer comprising oxygen and vertically stacked between the electrode and the ferroelectric layer, wherein the ferroelectric layer has a substantially uniform orthorhombic crystalline phase.   
     
     
         2 . The IC of  claim 1 , wherein the seed layer is configured to promote growth of orthorhombic phase crystals in the ferroelectric layer and inhibit growth of monoclinic phase crystals in the ferroelectric layer. 
     
     
         3 . The IC of  claim 1 , further comprising:
 an inter-diffusion region between the seed layer and the electrode, wherein the inter-diffusion region is configured to prevent a formation of charges at an interface of the seed layer and the electrode.   
     
     
         4 . The IC of  claim 1 , further comprising:
 a semiconductor layer over the ferroelectric layer; and   a pair of source/drain contacts laterally separated and respectively on opposite sides of the semiconductor layer.   
     
     
         5 . The IC of  claim 4 , wherein the pair of source/drain contacts are disposed on an opposite side of the semiconductor layer as the electrode. 
     
     
         6 . The IC of  claim 4 , wherein the pair of source/drain contacts are disposed on a same side of the semiconductor layer as the electrode. 
     
     
         7 . The IC of  claim 1 , further comprising:
 a semiconductor layer over the ferroelectric layer, wherein the semiconductor layer is amorphous Indium-Gallium-Zinc-Oxide.   
     
     
         8 . The IC of  claim 1 , wherein the seed layer is tantalum oxide and the ferroelectric layer is hafnium zirconium oxide. 
     
     
         9 . An integrated circuit (IC), comprising:
 a lower electrode disposed over a substrate, wherein the lower electrode comprises a first conductive material;   a seed layer arranged on the lower electrode, wherein the seed layer comprises oxygen and the first conductive material;   a ferroelectric layer arranged on the seed layer;   a semiconductor channel layer over the ferroelectric layer; and   source/drain contacts disposed on the semiconductor channel layer and laterally separated from one another.   
     
     
         10 . The IC of  claim 9 , wherein the lower electrode is tantalum nitride, the seed layer is tantalum oxide, the ferroelectric layer is hafnium zirconium oxide, and the semiconductor channel layer is Indium-Gallium-Zinc-Oxide. 
     
     
         11 . The IC of  claim 9 , wherein the seed layer has a predominantly crystalline phase. 
     
     
         12 . The IC of  claim 9 , wherein the seed layer completely covers an upper surface of the lower electrode and a lower surface of the ferroelectric layer. 
     
     
         13 . The IC of  claim 9 , wherein the seed layer continuously extends from a bottom surface physically contacting the lower electrode to a top surface physically contacting the ferroelectric layer. 
     
     
         14 . The IC of  claim 9 , wherein the lower electrode and the seed layer comprise tantalum. 
     
     
         15 . The IC of  claim 9 , wherein the seed layer comprises a thermal tantalum oxide. 
     
     
         16 . An integrated circuit (IC), comprising:
 an electrode disposed over a substrate;   a seed structure disposed on the electrode;   a ferroelectric structure disposed on the seed structure, wherein the seed structure is configured to promote growth of orthorhombic phase crystals in the ferroelectric structure and wherein the ferroelectric structure has a predominately orthorhombic crystal phase; and   an upper conductor disposed over the ferroelectric structure.   
     
     
         17 . The IC of  claim 16 , wherein the electrode and the seed structure comprise a same conductive material. 
     
     
         18 . The IC of  claim 16 , wherein the electrode comprises tantalum nitride and the seed structure comprises tantalum oxide. 
     
     
         19 . The IC of  claim 16 , further comprising:
 semiconductor layer arranged over the substrate;   an insulating layer arranged over the semiconductor layer, wherein the electrode is separated from the semiconductor layer by the insulating layer; and   source/drain contacts disposed on doped regions within the semiconductor layer and laterally separated from opposing sides of the electrode by an inter-level dielectric structure.   
     
     
         20 . The IC of  claim 19 , wherein the source/drain contacts vertically extend from the doped regions to an upper surface of the upper conductor.