Composite deep trench isolation structure in an image sensor

Abstract

In some embodiments, the present disclosure relates to an integrated chip that includes a first image sensing element and a second image sensing element arranged over a substrate. A first micro-lens is arranged over the first image sensing element, and a second micro-lens is arranged over the second image sensing element. A composite deep trench isolation structure is arranged between the first and second image sensing elements. The composite deep trench isolation structure includes a lower portion arranged over the substrate and an upper portion arranged over the lower portion. The lower portion includes a first material, and the upper portion includes a second material that has a lower reflectivity than the first material.

What is claimed is: 
     
         1 . An integrated chip, comprising:
 a first image sensing element arranged over a substrate;   a first micro-lens arranged over the first image sensing element;   a second image sensing element arranged over the substrate;   a second micro-lens arranged over the second image sensing element; and   a composite deep trench isolation structure arranged between the first and second image sensing elements and comprising:
 a lower portion arranged over the substrate and comprising a first material, and 
 an upper portion arranged over the lower portion and comprising a second material that has a lower reflectivity than the first material. 
   
     
     
         2 . The integrated chip of  claim 1 , further comprising:
 an interconnect structure coupled to the first and second image sensing elements and arranged between the substrate and the first and second image sensing elements.   
     
     
         3 . The integrated chip of  claim 1 , wherein the lower portion has a first height and the upper portion has a second height, wherein the first image sensing element has a third height, wherein a sum of the first and second heights is about equal the third height, and wherein the first height is at least 50 percent of the third height. 
     
     
         4 . The integrated chip of  claim 1 , wherein a bottommost surface of the upper portion of the composite deep trench isolation structure is below an uppermost surface of the first image sensing element. 
     
     
         5 . The integrated chip of  claim 1 , wherein the composite deep trench isolation structure continuously surrounds outermost sidewalls of the first and second image sensing elements. 
     
     
         6 . The integrated chip of  claim 1 , wherein the first material is a metal, and wherein the second material is a dielectric material. 
     
     
         7 . The integrated chip of  claim 1 , further comprising:
 a barrier layer arranged directly between the composite deep trench isolation structure and the first and second image sensing elements.   
     
     
         8 . The integrated chip of  claim 7 , wherein the barrier layer is also arranged directly between the upper and lower portions of the composited deep trench isolation structure. 
     
     
         9 . An integrated chip comprising:
 a plurality of image sensing elements arranged over or within a substrate;   processing circuitry coupled to the plurality of image sensing elements; and   a composite deep trench isolation structure arranged over or within the substrate, separating the plurality of image sensing elements from one another, and comprising:
 a lower portion comprising a first material having a first reflectivity, and 
 an upper portion comprising a second material having a second reflectivity less than the first reflectivity, 
 wherein the upper portion of the composite deep trench isolation structure has a bottommost surface arranged below topmost surfaces of the plurality of image sensing elements. 
   
     
     
         10 . The integrated chip of  claim 9 , wherein the upper portion of the composite deep trench isolation structure directly contacts the lower portion of the composite deep trench isolation structure. 
     
     
         11 . The integrated chip of  claim 9 , wherein the composite deep trench isolation structure continuously surrounds outer sidewalls of respective ones of the plurality of image sensing elements. 
     
     
         12 . The integrated chip of  claim 9 , wherein the lower portion of the composite deep trench isolation structure has a larger thickness than the upper portion of the composite deep trench isolation structure. 
     
     
         13 . The integrated chip of  claim 9 , further comprising:
 a passivation layer arranged directly on outermost sidewalls of the image sensing elements; and   a barrier layer arranged directly on the passivation layer and outermost sidewalls of the composite deep trench isolation structure.   
     
     
         14 . The integrated chip of  claim 13 , wherein the barrier layer is arranged directly between the upper and lower portions of the composite deep trench isolation structure. 
     
     
         15 . The integrated chip of  claim 13 , wherein the barrier layer and the passivation layer are arranged below a bottommost surface of the composite deep trench isolation structure. 
     
     
         16 . An integrated chip, comprising:
 a pixel region within a substrate, wherein the substrate comprises sidewalls that form one or more trenches along opposing sides of the pixel region;   a barrier disposed within the one or more trenches and lining the sidewalls of the substrate;   a metal disposed within the one or more trenches and lining interior sidewalls of the barrier, wherein the barrier separates the metal from the substrate; and   a dielectric disposed within the one or more trenches over the metal and lining the interior sidewalls of the barrier.   
     
     
         17 . The integrated chip of  claim 16 , wherein the barrier vertically extends past a top of the metal. 
     
     
         18 . The integrated chip of  claim 16 , wherein the dielectric physically contacts the metal along an interface that is below a top of the barrier. 
     
     
         19 . The integrated chip of  claim 16 , wherein opposing outermost sidewalls of the metal contact the interior sidewalls of the barrier. 
     
     
         20 . The integrated chip of  claim 16 , wherein the metal has a top surface that continuously extends between outermost sidewalls of the metal and that contacts a bottommost surface of the dielectric.