Enhanced design for image sensing technology

Abstract

The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.

What is claimed is: 
     
         1 . An integrated chip, comprising:
 an image sensing element disposed within a substrate;   a gate structure disposed along a front-side of the substrate;   wherein a back-side of the substrate comprises one or more first angled surfaces defining a central diffuser disposed over the image sensing element; and   wherein the back-side of the substrate further comprises second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser, the plurality of peripheral diffusers are a smaller size than the central diffuser.   
     
     
         2 . The integrated chip of  claim 1 , wherein the central diffuser has a greater maximum width than respective ones of the plurality of peripheral diffusers. 
     
     
         3 . The integrated chip of  claim 1 , wherein the central diffuser has a greater maximum depth than respective ones of the plurality of peripheral diffusers. 
     
     
         4 . The integrated chip of  claim 1 , wherein the plurality of peripheral diffusers surround the central diffuser along a first direction and along a second direction that is perpendicular to the first direction. 
     
     
         5 . The integrated chip of  claim 1 , further comprising:
 a second central diffuser laterally surrounded by the plurality of peripheral diffusers, wherein the second central diffuser is larger than respective ones of the plurality of peripheral diffusers.   
     
     
         6 . The integrated chip of  claim 1 ,
 wherein the one or more first angled surfaces meet at a first point that is at a bottom of the central diffuser; and   wherein one or more of the second angled surfaces meet at a second point that is at a bottom of one of the plurality of peripheral diffusers.   
     
     
         7 . The integrated chip of  claim 1 ,
 wherein the image sensing element is disposed within a pixel region; and   wherein the central diffuser is closer to a center of the pixel region than the plurality of peripheral diffusers.   
     
     
         8 . The integrated chip of  claim 1 , further comprising:
 a micro-lens disposed along the back-side of the substrate, wherein the central diffuser is closer to a center of the micro-lens than respective ones of the plurality of peripheral diffusers.   
     
     
         9 . The integrated chip of  claim 8 , wherein the micro-lens has an f-number of greater than approximately f/3. 
     
     
         10 . The integrated chip of  claim 1 , wherein the back-side of the substrate is substantially flat between the central diffuser and the plurality of peripheral diffusers. 
     
     
         11 . An integrated chip, comprising:
 an image sensing element disposed within a pixel region of a semiconductor substrate;   a plurality of interconnect layers disposed within a dielectric structure along a front-side of the semiconductor substrate;   wherein the semiconductor substrate defines a first tapered cavity disposed along a back-side of the semiconductor substrate and within the pixel region;   wherein the semiconductor substrate further defines a plurality of second tapered cavities along the back-side of the semiconductor substrate and between the first tapered cavity and a perimeter of the pixel region; and   wherein the first tapered cavity has a first maximum width that is larger than maximum widths of the plurality of second tapered cavities.   
     
     
         12 . The integrated chip of  claim 11 , wherein the first tapered cavity is configured to be disposed directly below a center of an overlying micro-lens. 
     
     
         13 . The integrated chip of  claim 11 , wherein the first tapered cavity is surrounded by the plurality of second tapered cavities along a first direction and along a second direction that is perpendicular to the first direction. 
     
     
         14 . The integrated chip of  claim 11 , wherein the image sensing element is configured to have a quantum efficiency that is greater than approximately 45% for incident radiation that intersects a line that is perpendicular to the back-side of the semiconductor substrate at angles of between approximately −20° and approximately 20°. 
     
     
         15 . The integrated chip of  claim 11 , wherein a quantum efficiency of the image sensing element has a maximum value for incident radiation that intersects a line that is perpendicular to the back-side of the semiconductor substrate at angles of between approximately −10° and approximately 10°. 
     
     
         16 . The integrated chip of  claim 11 , wherein the plurality of second tapered cavities are substantially symmetric about a center of the first tapered cavity as viewed in a top-view of the first tapered cavity. 
     
     
         17 . The integrated chip of  claim 11 , further comprising:
 one or more dielectric materials disposed within one or more isolation trenches arranged within the semiconductor substrate along opposing sides of the pixel region, wherein the first tapered cavity and the plurality of second tapered cavities are laterally surrounded by the one or more isolation trenches.   
     
     
         18 . The integrated chip of  claim 11 , wherein the first tapered cavity laterally extends past opposing sides of a first one of the plurality of second tapered cavities along a first direction and laterally extends past opposing sides of a second one of the plurality of second tapered cavities along a second direction that is perpendicular to the first direction. 
     
     
         19 . An integrated chip, comprising:
 an image sensing element within a pixel region of a substrate;   a plurality of interconnects within a dielectric structure along a first side of the substrate;   a central diffuser arranged along a second side of the substrate, the central diffuser being formed by a first pair of angled sidewalls of the substrate as viewed along a cross-sectional view;   a plurality of peripheral diffusers laterally surrounding the central diffuser and respectively formed by a second pair of angled sidewalls of the substrate as viewed along the cross-sectional view, wherein the second side of the substrate comprises a substantially flat surface laterally extending between the central diffuser and an adjacent one of the plurality of peripheral diffusers; and   wherein the central diffuser has a greater width and depth than respective ones of the plurality of peripheral diffusers.   
     
     
         20 . The integrated chip of  claim 19 , further comprising:
 a second central diffuser surrounded by the plurality of peripheral diffusers, wherein the second central diffuser has a larger size than the respective ones of the plurality of peripheral diffusers; and   wherein a third sidewall of the substrate that forms the second central diffuser intersects one of the first pair of angled sidewalls of the substrate at a point vertically below the substantially flat surface.