Integrated circuit having latch-up immunity

Abstract

An integrated circuit includes a semiconductor substrate, first tap regions, second tap regions, and first gate structures. The semiconductor substrate includes a first active region. The first and second tap regions in the semiconductor substrate and on opposite sides of the first active region. The first gate structures are over the first active region. A distance between the first tap region and a first one of the first gate structures adjacent the first tap region is greater than a distance between the second tap region and a second one of the first gate structures adjacent the second tap region.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 a semiconductor substrate comprising a first active region;   a first tap region and a second tap region in the semiconductor substrate and on opposite sides of the first active region; and   a plurality of first gate structures over the first active region, wherein a distance between the first tap region and a first one of the first gate structures adjacent the first tap region is greater than a distance between the second tap region and a second one of the first gate structures adjacent the second tap region.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the semiconductor substrate further comprises a second active region, wherein a length of the second active region is greater than a length of the first active region, and the integrated circuit further comprises:
 a third tap region and a fourth tap region in the semiconductor substrate and on opposite sides of the second active region; and   a plurality of second gate structures over the second active region.   
     
     
         3 . The integrated circuit of  claim 2 , wherein a distance between the third tap region and a first one of the second gate structures adjacent the third tap region is substantially equal to a distance between the fourth tap region and a second one of the second gate structures adjacent the fourth tap region. 
     
     
         4 . The integrated circuit of  claim 2 , wherein the first active region comprises a well having a different conductive type than that of a well of the second active region. 
     
     
         5 . The integrated circuit of  claim 1 , wherein a length of the first tap region is the same as a length of the second tap region. 
     
     
         6 . The integrated circuit of  claim 1 , wherein opposite ends of the first tap region are aligned with the first active region along a direction that the first active region extends along. 
     
     
         7 . The integrated circuit of  claim 1 , wherein the distance between the first tap region and the first one of the first gate structures adjacent the first tap region is greater than a width of the first gate structures. 
     
     
         8 . The integrated circuit of  claim 1 , wherein the semiconductor substrate further comprises a third active region, wherein the first tap region is on a first side of the third active region, and the integrated circuit further comprises:
 a plurality of third gate structures over the third active region, wherein a distance between the first tap region and a first one of the third gate structures adjacent the first tap region is greater than the distance between the second tap region and the second one of the first gate structures adjacent the second tap region.   
     
     
         9 . The integrated circuit of  claim 8 , wherein the first active region comprises a well having a same conductive type as a well of the third active region. 
     
     
         10 . The integrated circuit of  claim 8 , further comprising:
 a fifth tap region on a second side of the third active region, wherein the distance between the first tap region and the first one of the third gate structures adjacent the first tap region is greater than a distance between the fifth tap region and a second one of the third gate structures adjacent the fifth tap region.   
     
     
         11 . An integrated circuit, comprising:
 a semiconductor substrate comprising a first active region;   a first tap region and a second tap region in the semiconductor substrate and on opposite sides of the first active region; and   a plurality of first gate structures over the first active region, wherein a distance between the first tap region and one of the first gate structures adjacent the first tap region is greater than a width of the first gate structures.   
     
     
         12 . The integrated circuit of  claim 11 , further comprising:
 a plurality of source/drain regions adjoining the first gate structures, wherein the distance between the first tap region and said one of the first gate structures adjacent the first tap region is greater than a sum of the width of the first gate structures and a width of the source/drain regions.   
     
     
         13 . The integrated circuit of  claim 11 , wherein the semiconductor substrate further comprises a second active region, wherein a length of the second active region is greater than a length of the first active region, and the integrated circuit further comprises:
 a third tap region and a fourth tap region in the semiconductor substrate and on opposite sides of the second active region; and   a plurality of second gate structures over the second active region.   
     
     
         14 . The integrated circuit of  claim 13 , wherein the first and second active regions extend along a first direction, and the second tap region is aligned with the fourth tap region along a second direction perpendicular to the first direction in a top view. 
     
     
         15 . The integrated circuit of  claim 11 , wherein the semiconductor substrate further comprises a third active region, wherein the first tap region is on a side of the third active region, and the integrated circuit further comprises:
 a plurality of third gate structures over the third active region, wherein a distance between the first tap region and one of the third gate structures adjacent the first tap region is greater than the width of the first gate structures.   
     
     
         16 . The integrated circuit of  claim 15 , further comprising:
 a plurality of source/drain regions adjoining the first gate structures, wherein the distance between the first tap region and said one of the third gate structures adjacent the first tap region is greater than a sum of the width of the first gate structures and a width of the source/drain regions.   
     
     
         17 . An integrated circuit, comprising:
 a semiconductor substrate comprising a first active region and a second active region;   a first tap region and a second tap region in the semiconductor substrate and on opposite sides of the first active region;   a plurality of first gate structures over the first active region and between the first and second tap regions;   a third tap region and a fourth tap region in the semiconductor substrate and on opposite sides of the second active region; and   a plurality of second gate structures over the second active region, wherein a distance between the first tap region and one of the first gate structures adjacent the first tap region is greater than a distance between the fourth tap region and a first one of the second gate structures adjacent the fourth tap region.   
     
     
         18 . The integrated circuit of  claim 17 , wherein a length of the second active region is greater than a length of the first active region. 
     
     
         19 . The integrated circuit of  claim 17 , wherein the first and second active regions extend along a first direction, and the second tap region is aligned with the fourth tap region along a second direction perpendicular to the first direction in a top view. 
     
     
         20 . The integrated circuit of  claim 17 , wherein the distance between the first tap region and said one of the first gate structures adjacent the first tap region is greater than a distance between the third tap region and a second one of the second gate structures adjacent the third tap region.