Preventing gate-to-contact bridging by reducing contact dimensions in finfet sram

Abstract

A static random access memory (SRAM) cell includes a first gate and a second gate each extending in a first direction. A first gap separates the first gate from the second gate in the first direction. The SRAM cell includes a Vcc contact extending in the first direction. A second gap separates the Vcc contact and the first gate in a second direction perpendicular to the first direction. No segment of the Vcc contact overlaps with the first gap in the first direction. The SRAM cell includes a Vss contact extending in the first direction. A third gap separates the Vss contact from the first gate in the second direction. A segment of the Vss contact is disposed to the first gap. The Vss contact is smaller than the Vcc contact in the second direction.

What is claimed is: 
     
         1 . A method, comprising:
 receiving a computer file, the computer file specifying a layout for a circuit that includes:
 a first gate extending in a first direction; 
 a second gate extending in the first direction, the second gate being separated from the first gate in the first direction by a gap; 
 a first contact extending in the first direction; and 
 a second contact extending in the first direction, wherein the second contact is located closer to the gap than the first contact; and 
   generating a photomask design based on the computer file, wherein the second contact in the photomask design has a reduced size in a second direction different from the first direction.   
     
     
         2 . The method of  claim 1 , wherein the receiving of the computer file comprises receiving the computer file in a graphical database system (GDS) format. 
     
     
         3 . The method of  claim 1 , wherein the generating the photomask design is performed without reducing a size of the second contact in the first direction. 
     
     
         4 . The method of  claim 1 , wherein the computer file specifies the layout for a static random access memory (SRAM) device that includes a plurality of Vcc contacts, a plurality of bit-line (BL) contacts, a plurality of Vss contacts, and a plurality of node contacts. 
     
     
         5 . The method of  claim 4 , wherein the generating of the photomask design comprises reducing a size of one of the Vss contacts as the second contact in the second direction without affecting a size of one of the Vcc contacts as the first contact in either the first direction or the second direction. 
     
     
         6 . The method of  claim 5 , wherein the generating of the photomask design further comprises reducing a size of at least one of the node contacts in the second direction. 
     
     
         7 . The method of  claim 6 , wherein the reducing the size of the at least one of the node contacts comprises reducing a size of a first node contact from a first side and reducing a size of a second node contact from a second side opposite the first side. 
     
     
         8 . The method of  claim 6 , wherein the node contact and the Vss contact are located on opposite sides of the first gate in the second direction. 
     
     
         9 . The method of  claim 6 , wherein the node contact is located closer to the gap than the Vcc contact in the first direction. 
     
     
         10 . The method of  claim 1 , further comprising fabricating an integrated circuit (IC) device based on the photomask design. 
     
     
         11 . The method of  claim 1 , wherein the photomask design is generated by shrinking the second contact from opposite sides in the second direction. 
     
     
         12 . A method, comprising:
 accessing a computer file that includes a layout design for a circuit that includes:
 a first gate extending in a first direction; 
 a second gate extending in the first direction, wherein the second gate is spaced apart from the first gate in the first direction by a gap; 
 a first contact extending in the first direction; and 
 a second contact extending in the first direction, wherein the second contact is located closer to the gap than the first contact; and 
   generating a photomask design based on the computer file, wherein the photomask design is generated at least in part by shrinking the second contact in a second direction perpendicular to the first direction.   
     
     
         13 . The method of  claim 12 , wherein the generating the photomask design is performed without reducing a size of the second contact in the first direction. 
     
     
         14 . The method of  claim 12 , wherein:
 the layout design corresponds to a static random access memory (SRAM) device that includes a plurality of Vcc contacts, a plurality of bit-line (BL) contacts, a plurality of Vss contacts, and a plurality of node contacts;   the first contact is one of the Vcc contacts; and   the second contact is one of the Vss contacts.   
     
     
         15 . The method of  claim 12 , wherein the shrinking the second contact is performed from a first side of the second direction and a second side of the second direction opposite the first side. 
     
     
         16 . The method of  claim 12 , wherein the photomask design is generated without affecting a size of the first contact in either the first direction or the second direction. 
     
     
         17 . A method, comprising:
 receiving a first integrated circuit (IC) layout design that specifies a layout for a static random access memory (SRAM) device that includes:
 a first gate extending in a first direction; 
 a second gate extending in the first direction, the second gate being separated from the first gate in the first direction by a first gap; 
 a Vcc contact extending in the first direction; and 
 a Vss contact extending in the first direction, wherein the first gap is located closer to the Vss contact than to the Vcc contact; and 
   generating a second IC layout design based on the first IC layout design, wherein the second IC layout design is generated at least in part by shrinking a dimension of the Vss contact in a second direction different from the first direction.   
     
     
         18 . The method of  claim 17 , wherein the generating of the second IC layout design is performed without affecting a dimension of the Vss contact in the first direction and without affecting dimensions of the Vcc contact in either the first direction or the second direction. 
     
     
         19 . The method of  claim 17 , wherein:
 the SRAM device further includes a first node contact and a second node contact each extending in the first direction; and   the generating of the second IC layout design comprises shrinking dimensions of both the first node contact and the second node contact in the second direction.   
     
     
         20 . The method of  claim 17 , wherein the first IC layout design further includes a third gate extending in the first direction and separated from the first gate in the first direction by a second gap, and wherein the second gap is located closer to the Vcc contact than to the Vss contact.