Molded power semiconductor package

Abstract

A molded power semiconductor package includes: at least one first power electronics carrier having a metallization layer disposed on an electrically insulating substrate; a plurality of first power semiconductor dies attached to the metallization layer of the at least one first power electronics carrier; at least one second power electronics carrier having a metallization layer disposed on an electrically insulating substrate; a plurality of second power semiconductor dies attached to the metallization layer of the at least one second power electronics carrier; and a mold compound encasing the plurality of first power semiconductor dies and the plurality of second power semiconductor dies, and at least partly encasing the at least one first power electronics carrier and the at least one second power electronics carrier. The at least one first power electronics carrier and the at least one second power electronics carrier lie in a same plane.

What is claimed is: 
     
         1 . A molded power semiconductor package, comprising:
 at least one first power electronics carrier comprising a metallization layer disposed on an electrically insulating substrate;   a plurality of first power semiconductor dies attached to the metallization layer of the at least one first power electronics carrier;   at least one second power electronics carrier comprising a metallization layer disposed on an electrically insulating substrate;   a plurality of second power semiconductor dies attached to the metallization layer of the at least one second power electronics carrier; and   a mold compound encasing the plurality of first power semiconductor dies and the plurality of second power semiconductor dies, and at least partly encasing the at least one first power electronics carrier and the at least one second power electronics carrier,   wherein the at least one first power electronics carrier and the at least one second power electronics carrier lie in a same plane.   
     
     
         2 . The molded power semiconductor package of  claim 1 , wherein the plurality of first power semiconductor dies is attached to the metallization layer of a single first power electronics carrier, wherein a first subset and a second subset of the plurality of first power semiconductor dies are symmetrically arranged on the single first power electronics carrier about a longitudinal centerline of the molded power semiconductor package, wherein the plurality of second power semiconductor dies is attached to the metallization layer of a single second power electronics carrier, and wherein a first subset and a second subset of the plurality of second power semiconductor dies are symmetrically arranged on the single second power electronics carrier about the longitudinal centerline of the molded power semiconductor package. 
     
     
         3 . The molded power semiconductor package of  claim 1 , wherein first and second subsets of the plurality of first power semiconductor dies are attached to separate first power electronics carriers, wherein the separate first power electronics carriers are arranged symmetrically with respect to one another about a longitudinal centerline of the molded power semiconductor package, wherein first and second subsets of the plurality of second power semiconductor dies are attached to separate second power electronics carriers, and wherein the separate second power electronics carriers are arranged symmetrically with respect to one another about the longitudinal centerline of the molded power semiconductor package. 
     
     
         4 . The molded power semiconductor package of  claim 1 , wherein the plurality of first power semiconductor dies and the plurality of second power semiconductor dies are electrically coupled as a half bridge, wherein the plurality of first power semiconductor dies forms a low-side switch device of the half bridge, and wherein the plurality of second power semiconductor dies forms a high-side switch device of the half bridge. 
     
     
         5 . The molded power semiconductor package of  claim 1 , further comprising:
 at least one lead protruding from a first side face of the mold compound;   at least one lead protruding from a second side face of the mold compound opposite the first side face,   wherein a longitudinal centerline of the molded power semiconductor package extends between the first side face and the second side face of the mold compound.   
     
     
         6 . The molded power semiconductor package of  claim 1 , further comprising:
 a first structured metal frame disposed above the at least one first power electronics carrier and electrically connected to a load terminal of each power semiconductor die of the plurality of first power semiconductor dies; and   a second structured metal frame disposed above the at least one second power electronics carrier and electrically connected to a load terminal of each power semiconductor die of the plurality of second power semiconductor dies.   
     
     
         7 . The molded power semiconductor package of  claim 6 , wherein:
 a first subset and a second subset of the plurality of first power semiconductor dies are arranged on opposite sides of a longitudinal centerline of the molded power semiconductor package;   a first subset and a second subset of the plurality of second power semiconductor dies are arranged on the opposite sides of the longitudinal centerline;   the first structured metal frame comprises a first central part that extends along the longitudinal centerline, first branches each joined at a proximal end to the first central part and extending in parallel over the first subset of the plurality of first power semiconductor dies in a first lateral direction that is transverse to the longitudinal centerline, and second branches each joined at a proximal end to the first central part and extending in parallel over the second subset of the plurality of first power semiconductor dies in a second lateral direction opposite the first lateral direction; and   the second structured metal frame comprises a second central part that extends along the longitudinal centerline, third branches each joined at a proximal end to the second central part and extending in parallel over the first subset of the plurality of second power semiconductor dies in the first lateral direction, and fourth branches each joined at a proximal end to the second central part and extending in parallel over the second subset of the plurality of second power semiconductor dies in the second lateral direction.   
     
     
         8 . The molded power semiconductor package of  claim 7 , wherein:
 the first branches are vertically connected to a load terminal of each power semiconductor die included in the first subset of the plurality of first power semiconductor dies;   the second branches are vertically connected to a load terminal of each power semiconductor die included in the second subset of the plurality of first power semiconductor dies;   the third branches are vertically connected to a load terminal of each power semiconductor die included in the first subset of the plurality of second power semiconductor dies; and   the fourth branches are vertically connected to a load terminal of each power semiconductor die included in the second subset of the plurality of second power semiconductor dies.   
     
     
         9 . The molded power semiconductor package of  claim 7 , wherein:
 the first structured metal frame comprises a first additional branch that connects the first branches at a distal end of the first branches, and a second additional branch that connects the second branches at a distal end of the second branches; and   the second structured metal frame comprises a third additional branch that connects the third branches at a distal end of the third branches, and a fourth additional branch that connects the fourth branches at a distal end of the fourth branches.   
     
     
         10 . The molded power semiconductor package of  claim 7 , wherein:
 the first structured metal frame comprises a first gate metallization disposed in an opening formed in the first central part and that is electrically insulated from the first central part, the first branches, and the second branches;   the first gate metallization is electrically connected to a gate terminal of each power semiconductor die included in the plurality of first power semiconductor dies;   the second structured metal frame comprises a second gate metallization disposed in an opening formed in the second central part and that is electrically insulated from the second central part, the third branches, and the fourth branches; and   the second gate metallization is electrically connected to a gate terminal of each power semiconductor die included in the plurality of second power semiconductor dies.   
     
     
         11 . The molded power semiconductor package of  claim 10 , further comprising:
 a first press-fit pin attached to the first gate metallization and protruding through a front surface of the mold compound, the mold compound also having a back surface opposite the front surface and side faces extending between the front and back surfaces; and   a second press-fit pin attached to the second gate metallization and protruding through the front surface of the mold compound.   
     
     
         12 . The molded power semiconductor package of  claim 7 , further comprising:
 at least one printed circuit board (PCB) disposed in an opening formed in the first central part and in an opening formed in the second central part, wherein the at least one PCB has one or more first metal traces electrically connected to a gate terminal of each power semiconductor die included in the plurality of first power semiconductor dies and one or second more metal traces electrically connected to a gate terminal of each power semiconductor die included in the plurality of second power semiconductor dies; and/or   a first additional power electronics carrier disposed in an opening formed in the first central part and having a gate metallization electrically connected to a gate terminal of each power semiconductor die included in the plurality of first power semiconductor dies, and a second additional power electronics carrier disposed in an opening formed in the second central part and having a gate metallization electrically connected to a gate terminal of each power semiconductor die included in the plurality of second power semiconductor dies.   
     
     
         13 . The molded power semiconductor package of  claim 7 , wherein:
 the second structured metal frame comprises an additional branch at an end of the second central part that faces the first structured metal frame;   the additional branch extends in parallel with both the third branches and the fourth branches;   the additional branch is vertically connected to the metallization layer of the at least one first power electronics carrier.   
     
     
         14 . The molded power semiconductor package of  claim 13 , wherein:
 the metallization layer of the least one first power electronics carrier is electrically connected to a drain terminal of each power semiconductor die of the plurality of first power semiconductor dies;   the metallization layer of the least one second power electronics carrier is electrically connected to a drain terminal of each power semiconductor die of the plurality of second power semiconductor dies;   the first structured metal frame is electrically connected to a source terminal of each power semiconductor die of the plurality of first power semiconductor dies;   the second structured metal frame is electrically connected to a source terminal of each power semiconductor die of the plurality of second power semiconductor dies; and   the additional branch of the second structured metal frame forms a switch node connection between the drain terminal of each power semiconductor die of the plurality of first power semiconductor dies and the source terminal of each power semiconductor die of the plurality of second power semiconductor dies.   
     
     
         15 . The molded power semiconductor package of  claim 6 , wherein:
 a first subset and a second subset of the plurality of first power semiconductor dies are arranged on opposite sides of a longitudinal centerline of the molded power semiconductor package;   a first subset and a second subset of the plurality of second power semiconductor dies are arranged on the opposite sides of the longitudinal centerline of the molded power semiconductor package;   the first structured metal frame comprises a first central part that is wire bonded to a load terminal of each power semiconductor die included in the first power semiconductor dies; and   the second structured metal frame comprises a second central part that is wire bonded to a load terminal of each power semiconductor die included in the second power semiconductor dies.   
     
     
         16 . The molded power semiconductor package of  claim 15 , further comprising:
 a printed circuit board (PCB) disposed in an opening formed in the first central part and in the second central part, wherein the PCB has one or more first metal traces electrically connected to a gate terminal of each power semiconductor die included in the plurality of first power semiconductor dies, wherein the PCB has one or more second metal traces electrically connected to a gate terminal of each power semiconductor die included in the plurality of second power semiconductor dies; and/or   an additional power electronics carrier disposed in an opening formed in the first central part and in the second central part, wherein the additional power electronics carrier has a first gate metallization electrically connected to a gate terminal of each power semiconductor die included in the plurality of first power semiconductor dies, wherein the additional power electronics carrier has a second gate metallization electrically connected to a gate terminal of each power semiconductor die included in the plurality of second power semiconductor dies.   
     
     
         17 . The molded power semiconductor package of  claim 15 , wherein:
 the second structured metal frame comprises at least one branch at an end of the second central part that faces the first structured metal frame; and   the at least one branch is wire bonded to the metallization layer of the at least one first power electronics carrier.   
     
     
         18 . The molded power semiconductor package of  claim 17 , wherein:
 the metallization layer of the least one first power electronics carrier is electrically connected to a drain terminal of each power semiconductor die of the plurality of first power semiconductor dies;   the metallization layer of the least one second power electronics carrier is electrically connected to a drain terminal of each power semiconductor die of the plurality of second power semiconductor dies;   the first structured metal frame is wire bonded to a source terminal of each power semiconductor die of the plurality of first power semiconductor dies;   the second structured metal frame is wire bonded to a source terminal of each power semiconductor die of the plurality of second power semiconductor dies; and   the at least one branch of the second structured metal frame forms a switch node connection between the drain terminal of each power semiconductor die of the plurality of first power semiconductor dies and the source terminal of each power semiconductor die of the plurality of second power semiconductor dies.   
     
     
         19 . The molded power semiconductor package of  claim 6 , further comprising:
 a first power lead electrically connected to the metallization layer of the at least one second power electronics carrier and protruding from a first side face of the mold compound;   a second power lead electrically connected to the metallization layer of the at least one second power electronics carrier and protruding from the first side face of the mold compound,   wherein the first power lead flanks a first side of the first structured metal frame,   wherein the second power lead flanks a second side of the first structured metal frame opposite the first side.   
     
     
         20 . The molded power semiconductor package of  claim 19 , further comprising:
 a first press-fit pin attached to the first structured metal frame and protruding through a front surface of the mold compound, the mold compound also having a back surface opposite the front surface, the first and second side faces of the mold compound extending between the front and back surfaces; and   a second press-fit pin attached to the second structured metal frame and protruding through the front surface of the mold compound.   
     
     
         21 . The molded power semiconductor package of  claim 19 , further comprising:
 a first gate metallization embedded in the mold compound above the at least one first power electronics carrier and electrically connected to a gate terminal of each power semiconductor die included in the plurality of first power semiconductor dies;   a second gate metallization embedded in the mold compound above the at least one second power electronics carrier and electrically connected to a gate terminal of each power semiconductor die included in the plurality of second power semiconductor dies;   a first press-fit pin attached to the first gate metallization and protruding through a front surface of the mold compound, the mold compound also having a back surface opposite the front surface, the first and second side faces of the mold compound extending between the front and back surfaces; and   a second press-fit pin attached to the second gate metallization and protruding through the front surface of the mold compound.   
     
     
         22 . A molded power semiconductor package, comprising:
 a mold compound;   a plurality of first power semiconductor dies embedded in the mold compound;   a plurality of second power semiconductor dies embedded in the mold compound and electrically connected to the plurality of first power semiconductor dies to form a half bridge;   a first structured metal frame above the plurality of first power semiconductor dies and comprising a plurality of first parallel branches electrically connected to a frontside load terminal of a first group of the first power semiconductor dies arranged on a first side of a longitudinal centerline of the molded power semiconductor package and a plurality of second parallel branches electrically connected to a frontside load terminal of a second group of the first power semiconductor dies arranged on a second side of the longitudinal centerline opposite the first side; and   a second structured metal frame above the plurality of second power semiconductor dies and comprising a plurality of first parallel branches electrically connected to a frontside load terminal of a first group of the second power semiconductor dies arranged on the first side of the longitudinal centerline and a plurality of second parallel branches electrically connected to a frontside load terminal of a second group of the second power semiconductor dies arranged on the second side of the longitudinal centerline.   
     
     
         23 . The molded power semiconductor package of  claim 22 , further comprising:
 a first power lead for the half bridge protruding from a first side face of the mold compound;   a second power lead for the half bridge protruding from the first side face of the mold compound,   wherein the first power lead flanks a first side of the first structured metal frame,   wherein the second power lead flanks a second side of the first structured metal frame opposite the first side.   
     
     
         24 . The molded power semiconductor package of  claim 23 , wherein an end of the first structured metal frame protrudes from the first side face of the mold compound to form a ground lead for the half bridge, and/or wherein an end of the second structured metal frame protrudes from a second side face of the mold compound opposite the first side face to form a switch node lead for the half bridge. 
     
     
         25 . The molded power semiconductor package of  claim 23 , further comprising:
 a first press-fit pin attached to the first structured metal frame and protruding through a front surface of the mold compound, the mold compound also having a back surface opposite the front surface, the first and second side faces of the mold compound extending between the front and back surfaces; and   a second press-fit pin attached to the second structured metal frame and protruding through the front surface of the mold compound.   
     
     
         26 . The molded power semiconductor package of  claim 23 , further comprising:
 a first gate metallization embedded in the mold compound above the plurality of first power semiconductor dies and electrically connected to a gate terminal of each power semiconductor die included in the plurality of first power semiconductor dies;   a second gate metallization embedded in the mold compound above the plurality of second power semiconductor dies and electrically connected to a gate terminal of each power semiconductor die included in the plurality of second power semiconductor dies;   a first press-fit pin attached to the first gate metallization and protruding through a front surface of the mold compound, the mold compound also having a back surface opposite the front surface, the first and second side faces of the mold compound extending between the front and back surfaces; and   a second press-fit pin attached to the second gate metallization and protruding through the front surface of the mold compound.   
     
     
         27 . The molded power semiconductor package of  claim 23 , wherein the first power lead and the second power lead are each thicker than both the first structured metal frame and the second structured metal frame. 
     
     
         28 . The molded power semiconductor package of  claim 27 , wherein the first structured metal frame and the second structured metal frame are part of a first lead frame, wherein the first power lead and the second power lead are part of a second lead frame, wherein the second lead frame overlies and is attached to the first lead frame, and wherein the second lead frame is thicker than the first lead frame. 
     
     
         29 . The molded power semiconductor package of  claim 23 , further comprising:
 a ground lead for the half bridge protruding from the first side face of the mold compound and laterally interposed between the first power lead and the second power lead,   wherein the ground lead is vertically connected to the first structured metal frame and thicker than both the first structured metal frame and the second structured metal frame.   
     
     
         30 . The molded power semiconductor package of  claim 23 , further comprising:
 a switch node lead for the half bridge protruding from a first side face of the mold compound opposite the first side face,   wherein the switch node lead is vertically connected to the second structured metal frame and thicker than both the first structured metal frame and the second structured metal frame.   
     
     
         31 . The molded power semiconductor package of  claim 23 , further comprising:
 a plurality of metal strips or a single metal sheet connected at a first end to the first power lead and at a second end to the second power lead,   wherein the plurality of metal strips or single metal sheet spans the first structured metal frame.   
     
     
         32 . The molded power semiconductor package of  claim 23 , further comprising:
 a first metal strip or sheet connected at a first end to a first part of the first power lead and at a second end to a second end of the first power lead; and   a second metal strip or sheet connected at a first end to a first part of the second power lead and at a second end to a second end of the second power lead,   wherein the first metal strip or sheet spans the first structured metal frame between the first part and the second part of the first power lead,   wherein the second metal strip or sheet spans the first structured metal frame between the first part and the second part of the second power lead.   
     
     
         33 . The molded power semiconductor package of  claim 22 , wherein the plurality of first power semiconductor dies is equally distributed on both sides of the longitudinal centerline, and wherein the plurality of second power semiconductor dies is equally distributed on both sides of the longitudinal centerline.