Semiconductor packages and methods for forming the same

Abstract

Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and exposed on edge surfaces of the integrated circuit die. The edge interconnect features are configured to connect with other integrated circuit dies without going through an interposer. The semiconductor device may include two or more integrated circuit dies with edge interconnect features and connected through one or more inter-chip connectors formed between the two or more integrated circuit dies. In some embodiments, the inter-chip connectors may be formed by a selective bumping process during packaging.

1 . A semiconductor package, comprising:
 a first integrated circuit die having a first cutting surface, wherein the first integrated circuit die comprises a first edge interconnect feature extending to the first cutting surface;   a second integrated circuit die having a second cutting surface, wherein the second integrated circuit die comprises a second edge interconnect feature extending to the second cutting surface; and   an inter-chip connector having a first end contacting the first edge interconnect feature and a second end contacting the second edge interconnect feature.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the first integrated circuit die further comprises a first interconnect structure, and the first edge interconnect feature is connected to the first interconnect structure. 
     
     
         3 . The semiconductor package of  claim 2 , wherein the first interconnect structure comprises:
 an IMD (inter metal dielectric) layer; and   a conductive feature embedded in the IMD layer, wherein an inner end of the first edge interconnect feature is connected to the conductive feature, and an outer end of the first edge interconnect feature extends to the first cutting surface of the first interconnect feature.   
     
     
         4 . The semiconductor package of  claim 3 , wherein the first interconnect structure further comprises a sealing ring, and the first edge interconnect feature extends through an opening in the sealing ring. 
     
     
         5 . The semiconductor package of  claim 4 , further comprising an encapsulant layer formed between the first integrated circuit die and the second integrated circuit die, and wherein the inter-chip connector is formed in the encapsulant layer. 
     
     
         6 . The semiconductor package of  claim 3 , wherein the first integrated circuit die further comprises a plurality of external contacts formed on the first interconnect structure. 
     
     
         7 . The semiconductor package of  claim 6 , further comprising an interposer substrate attached to the plurality of external contacts of the first integrated circuit die. 
     
     
         8 . A semiconductor package, comprising:
 a substrate;   a first integrated circuit die attached to the substrate, wherein the first integrated circuit die has a first cutting surface;   a second integrated circuit die attached to the substrate adjacent the first integrated circuit die, wherein the second integrated circuit die has a second cutting surface, and the first cutting surface faces the second cutting surface; and   a plurality of inter-chip connectors formed between the first integrated circuit die and second integrated circuit die, wherein a first end of each of the inter-chip connector contacts the first cutting surface and a second end of the inter-chip connector contacts the second cutting surface.   
     
     
         9 . The semiconductor package of  claim 8 , wherein the substrate is an interposer substrate, and the first integrated circuit die connected to the interposer substrate through a plurality of first external contacts. 
     
     
         10 . The semiconductor package of  claim 9 , further comprising an encapsulant layer, wherein the plurality of inter-chip connectors are embedded in the encapsulant layer. 
     
     
         11 . The semiconductor package of  claim 8 , wherein the first integrated circuit die comprises:
 one or more transistors;   an interconnect structure comprising two or more IMD layers formed over the one or more transistors; and   a plurality of edge interconnect features, wherein each of the plurality of edge interconnect feature has an inner end embedded in one of the two or more IMD layers and an outer end in contact with one of the plurality of the inter-chip connectors.   
     
     
         12 . The semiconductor package of  claim 11 , wherein the interconnect structure comprises a sealing ring formed in the two or more IMD layers, and the plurality of edge interconnect features extend through openings in the sealing ring. 
     
     
         13 . The semiconductor package of  claim 11 , wherein the first integrated circuit die has four cutting surfaces including the first cutting surface, and the plurality of edge interconnect features are symmetrically distributed along all of the four cutting surfaces of the first integrated circuit die. 
     
     
         14 . The semiconductor package of  claim 13 , further comprises a plurality of conductive bumping features in contact with the plurality of edge interconnect features on all of the four cutting surfaces of the first integrated circuit die. 
     
     
         15 . A semiconductor package, comprising:
 a first integrated circuit die having a first edge interconnect feature;   a second integrated circuit die having a second edge interconnect feature, wherein the first and second integrated circuit dies are positioned adjacent to each other such that the first edge conductive feature faces the second edge conductive feature; and   an inter-chip connector formed between the first edge conductive feature and the second edge conductive feature.   
     
     
         16 . The semiconductor package of  claim 15 , further comprising an encapsulant layer formed between the first integrated circuit die and the second integrated circuit die, and the inter-chip connector is embedded in the encapsulant layer. 
     
     
         17 . The semiconductor package of  claim 16 , wherein the inter-chip connector is formed by an electroless deposition process prior to deposition of the encapsulate layer. 
     
     
         18 . The semiconductor package of  claim 15 , further comprising an interposer substrate attached to the plurality of external contacts of the first integrated circuit die. 
     
     
         19 . The semiconductor package of  claim 15 , wherein the first integrated circuit die comprises:
 a device layer including one or more semiconductor devices; and   an IMD layer formed over the device layer, wherein the first edge interconnect feature is formed in the IMD layer.   
     
     
         20 . The semiconductor package of  claim 19 , where the first integrated circuit die further comprises a sealing ring in the IMD layer adjacent a perimeter of the first integrated circuit die, the sealing ring has an opening, and the first edge interconnect feature extends through the opening.