Vertical memory structure with air gaps and method for preparing the same

Abstract

The present disclosure provides a vertical memory structure including a semiconductor stack, a contact plug, gate electrodes and air gap structures. The semiconductor stack includes a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate. The contact plug is disposed over the lower semiconductor pattern structure. The contact plug includes a lower portion and a middle portion over the lower portion. A width of the middle portion is less than a width of the lower portion. The gate electrodes are surrounding a sidewall of the semiconductor stack. The air gap structures are disposed at outer sides of the plurality of gate electrode respectively.

What is claimed is: 
     
         1 . A vertical memory structure, comprising:
 a semiconductor stack, comprising:
 a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate; 
   a contact plug, disposed over the lower semiconductor pattern structure, comprising:
 a lower portion; and 
 a middle portion over the lower portion, wherein a width of the middle portion is less than a width of the lower portion; 
   a plurality of gate electrodes surrounding a sidewall of the semiconductor stack; and   a plurality of air gap structures disposed at outer sides of the plurality of gate electrode respectively.   
     
     
         2 . The vertical memory structure of  claim 1 , wherein the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction. 
     
     
         3 . The vertical memory structure of  claim 1 , wherein the contact plug further comprises:
 an upper portion over the middle portion, wherein a width of the upper portion is greater than the width of the middle portion.   
     
     
         4 . The vertical memory structure of  claim 3 , wherein the width of the upper portion is greater than the width of the lower portion. 
     
     
         5 . The vertical memory structure of  claim 3 , wherein the width of the upper portion is equal to the width of the lower portion. 
     
     
         6 . The vertical memory structure of  claim 3 , wherein the lower portion, the middle portion and the upper portion are a continuous single structure. 
     
     
         7 . The vertical memory structure of  claim 1 , wherein each of the plurality of air gap structures comprises:
 an air gap; and   a liner layer enclosing the air gap.   
     
     
         8 . The vertical memory structure of  claim 1 , wherein the lower semiconductor pattern structure comprises:
 a first undoped semiconductor pattern;   a doped semiconductor pattern over the first undoped semiconductor pattern; and   a second undoped semiconductor pattern over the doped semiconductor pattern.   
     
     
         9 . The vertical memory structure of  claim 8 , wherein the lower semiconductor pattern structure further comprises:
 a first diffusion prevention pattern, disposed between the first undoped semiconductor pattern and the doped semiconductor pattern; and   a second diffusion prevention pattern, disposed between the doped semiconductor pattern and the second undoped semiconductor pattern.   
     
     
         10 . The vertical memory structure of  claim 9 , wherein the first diffusion prevention pattern and the second diffusion prevention pattern comprise carbon. 
     
     
         11 . The vertical memory structure of  claim 10 , wherein the second diffusion prevention pattern further comprises boron. 
     
     
         12 . The vertical memory structure of  claim 8 , further comprising:
 an impurity layer over the substrate,   wherein the impurity layer is in contact with the doped semiconductor pattern.   
     
     
         13 . The vertical memory structure of  claim 12 , wherein the impurity layer comprises p-type impurities. 
     
     
         14 . The vertical memory structure of  claim 8 , wherein the semiconductor stack further comprises:
 an upper semiconductor pattern extending in the first direction on the lower semiconductor pattern structure.   
     
     
         15 . The vertical memory structure of  claim 14 , wherein the upper semiconductor pattern comprises:
 a charge storage structure;   an upper channel structure;   a filling pattern, wherein the upper channel structure and the filling pattern are penetrating through the charge storage structure to the second undoped semiconductor pattern; and   a capping pattern, disposed over the charge storage structure, the upper channel structure and the filling pattern.   
     
     
         16 . The vertical memory structure of  claim 15 , wherein the lower portion is in contact with the capping pattern, and a width of the lower portion is less than a width of the capping pattern. 
     
     
         17 . The vertical memory structure of  claim 1 , further comprising:
 an impurity region, disposed in the substrate;   a common source/drain line (CSL), protruding from the upper surface of the substrate in a first direction into the impurity region; and   a spacer, surrounding a sidewall of the common CSL,   wherein the common CSL is in contact with the impurity region.   
     
     
         18 . The vertical memory structure of  claim 1 , further comprising:
 an insulating interlayer, disposed over the common CSL, and   a bit line, disposed over the insulating interlayer,   wherein the bit line covers the contact plug, and the insulating interlayer surrounds the middle portion.   
     
     
         19 . A vertical memory structure, comprising:
 a semiconductor stack over a substrate;   a contact plug, disposed over the semiconductor stack, comprising:
 a barrier layer, wherein the barrier layer comprises aluminum fluoride and zinc oxide; 
 a connector, disposed over the barrier layer; 
   a plurality of gate electrodes surrounding a sidewall of the semiconductor stack, wherein the plurality of gate electrodes are at a plurality of levels, respectively, so as to be spaced apart from each other in a first direction perpendicular to a top surface of the substrate;   a plurality of air gap structures disposed at outer sides of the plurality of gate electrode respectively; and   a common source/drain line (CSL), protruding from an upper surface of the substrate.   
     
     
         20 . The vertical memory structure of  claim 19 , wherein the semiconductor stack comprises:
 a lower semiconductor pattern structure filling a recess on the substrate and protruding from the upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate; and   an upper semiconductor pattern extending in the first direction on the lower semiconductor pattern structure.