Semiconductor device and method for fabricating the same

Abstract

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.

What is claimed is: 
     
         1 . A method for fabricating semiconductor device, comprising:
 forming a gate structure on a substrate;   forming a spacer around the gate structure, wherein the spacer comprises:
 an offset spacer adjacent to the gate structure; and 
 a main spacer adjacent to the offset spacer; 
   forming a first contact etch stop layer (CESL) around the spacer and on and directly contacting the substrate; and   forming a second CESL around the spacer and on and directly contacting the offset spacer, the main spacer, and the first CESL.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming the first CESL on the gate structure;   forming a mask layer on the first CESL;   removing part of the mask layer;   removing part of the first CESL;   forming the second CESL on the mask layer and the gate structure; and   removing part of the second CESL.   
     
     
         3 . The method of  claim 2 , wherein the step of remove part of the mask layer comprises:
 performing a planarizing process to remove part of the mask layer so that the top surfaces of the mask layer and the first CESL are coplanar; and   performing an etching process to remove part of the mask layer so that the top surface of the mask layer is lower than a top surface of the gate structure.   
     
     
         4 . The method of  claim 2 , wherein a top surface of the first CESL is higher than a top surface of the mask layer. 
     
     
         5 . The method of  claim 2 , wherein the gate structure comprises a gate material layer, a first hard mask on the gate material layer, and a second hard mask on the first hard mask, the method further comprising:
 removing part of the mask layer so that the top surface of the mask layer is lower than a top surface of the gate material layer.   
     
     
         6 . The method of  claim 5 , wherein a bottom surface of the second CESL is lower than a top surface of the gate material layer. 
     
     
         7 . The method of  claim 1 , further comprising performing a replacement metal gate (RMG) process to transform the gate structure into metal gate after forming the second CESL. 
     
     
         8 . The method of  claim 1 , further comprising forming a source/drain region adjacent to two sides of the spacer in the substrate before forming the first CESL. 
     
     
         9 . The method of  claim 1 , wherein the first CESL and the second CESL comprise different material. 
     
     
         10 . The method of  claim 1 , wherein the first CESL and the second CESL comprise different dielectric constant. 
     
     
         11 . The method of  claim 1 , wherein a dielectric constant of the first CESL is lower than a dielectric constant of the second CESL.