Gate stack dipole compensation for threshold voltage definition in transistors

Abstract

A semiconductor structure includes a semiconductor substrate, with first, second, and third field effect transistors (FETs) formed on the substrate. A gate of the first FET includes a gate electrode, a first work function metal (WFM) layered with a first interfacial layer (IL) and a first high-k dielectric (HK); a gate of the second FET includes the first WFM layered with a second IL, a second HK, and a first dipole material; and a gate of the third FET includes the first WFM layered with a third IL, a third HK, the first dipole material, and a second dipole material. The first FET does not include the first dipole material and does not include the second dipole material, and the second FET does not include the second dipole material.

What is claimed is: 
     
         1 . A semiconductor structure comprising:
 a semiconductor substrate;   a first p-type field effect transistor (FET) formed on the substrate, wherein the first pFET has a first threshold voltage (Vt 0 ) and a gate of the first pFET comprises a gate electrode, a first work function metal (WFM) layered with a first interfacial layer (IL) and a first high-k dielectric (HK);   a second pFET formed on the substrate, wherein the second pFET has a second threshold voltage (Vt 1 ) and a gate of the second pFET comprises the first WFM layered with a second IL, a second HK, and a first dipole material; and   a third pFET formed on the substrate, wherein the third pFET has a third threshold voltage (Vt 2 ) and a gate of the third pFET comprises the first WFM layered with a third IL, a third HK, the first dipole material, and a second dipole material,   wherein, the first nFET does not include the first dipole material and does not include the second dipole material, and the second nFET does not include the second dipole material, such that |Vt 0 |<|Vt 2 |<|Vt 1 |.   
     
     
         2 . The semiconductor structure of  claim 1 , further comprising:
 a fourth pFET formed on the substrate, wherein the fourth pFET has a threshold voltage Vt 3  and a gate of the fourth pFET comprises the first WFM layered with a fourth IL and a fourth HK, wherein |Vt 3 |<|Vt 0 |, and the fourth pFET has only the second dipole material between the fourth IL and the fourth HK and inside the fourth IL and the fourth HK.   
     
     
         3 . The semiconductor structure of  claim 1 , wherein:
 the first dipole material is present in the second IL and the second HK on the second pFET and in the third IL and the third HK on the third pFET.   
     
     
         4 . The semiconductor structure of  claim 3 , wherein:
 the second dipole material is present in the third IL and the third HK on the third pFET.   
     
     
         5 . The semiconductor structure of  claim 1 , wherein the first dipole material shifts threshold voltage toward a conduction band of a semiconductor. 
     
     
         6 . The semiconductor structure of  claim 5 , wherein the first dipole material comprises a material selected from a list consisting of: lanthanum, yttrium, magnesium, gadolinium. 
     
     
         7 . The semiconductor structure of  claim 1 , wherein the second dipole material shifts threshold voltage toward a valence band of a semiconductor. 
     
     
         8 . The semiconductor structure of  claim 7 , wherein the second dipole material comprises a material selected from a list consisting of: aluminum, manganese, titanium. 
     
     
         9 . A semiconductor structure comprising:
 a semiconductor substrate;   a first field effect transistor (FET) formed on the substrate, the first field effect transistor being an n-type field effect transistor (nFET), wherein the nFET has a first threshold voltage (Vt 0 ) and a gate of the nFET comprises a gate electrode and a first work function metal (WFM) layered with a first interfacial layer (IL), a first high-k dielectric (HK), and a first dipole material; and   a second field effect transistor (FET) formed on the substrate, the second field effect transistor being a p-type FET (pFET), wherein the pFET has a second threshold voltage (Vt 1 ) and a gate of the pFET comprises a gate electrode and a first work function metal (WFM) layered with a second interfacial layer, a second high-k dielectric, and a second dipole material.