Mechanism for interrupting and resuming execution on an unprotected pipeline processor

Abstract

Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, beginning execution of the first instruction, receiving one or more second instructions for execution on the instruction execution pipeline, the one or more second instructions associated with a higher priority task than the first instruction, storing a register state associated with the execution of the first instruction in one or more registers of a capture queue associated with the instruction execution pipeline, copying the register state from the capture queue to a memory, determining that the one or more second instructions have been executed, copying the register state from the memory to the one or more registers of the capture queue, and restoring the register state to the instruction execution pipeline from the capture queue.

What is claimed is: 
     
         1 . A circuit device comprising:
 a processor that includes:
 a functional unit that includes a set of pipeline stages; 
 a capture queue associated with the functional unit; 
 a scoreboard coupled to the functional unit and to the capture queue and configured to:
 store a lifetime tracking value associated with an expected number of cycles to execute an instruction; 
 decrement the lifetime tracking value based on execution of the instruction; 
 based on an interrupt, cause a state of the set of pipeline stages that is associated with the instruction to be stored in the capture queue; and 
 based on completion of the interrupt and on the lifetime tracking value: 
 cause the state to be restored to the set of pipeline stages; and 
 cause the execution of the instruction using the set of pipeline stages to be resumed. 
 
   
     
     
         2 . The circuit device of  claim 1 , wherein the processor includes a vector data path that includes the functional unit. 
     
     
         3 . The circuit device of  claim 1 , wherein the processor includes a scalar data path that includes the functional unit. 
     
     
         4 . The circuit device of  claim 1 , wherein:
 the capture queue is a first capture queue;   the processor includes a second capture queue; and   the scoreboard is configured to:
 based on the interrupt, cause the state of the set of pipeline stages to be stored in the second capture queue via the first capture queue; and 
 based on completion of the interrupt, cause the state to be restored to the set of pipeline stages to be restored from the second capture queue via the first capture queue. 
   
     
     
         5 . The circuit device of  claim 4 , wherein the processor includes a cache memory that includes the second capture queue. 
     
     
         6 . The circuit device of  claim 1 , wherein the scoreboard is configured to maintain the lifetime tracking value based on the set of pipeline stages being stalled. 
     
     
         7 . The circuit device of  claim 1 , wherein the set of pipeline stages are configured to write a result of the instruction when the lifetime tracking value is zero. 
     
     
         8 . The circuit device of  claim 1 , wherein:
 the functional unit is a first functional unit;   the set of pipeline stages is a first set of pipeline stages;   the capture queue is a first capture queue;   the lifetime tracking value is a first lifetime tracking value;   the processor includes:
 a second functional unit that includes a second set of pipeline stages; and 
 a second capture queue associated with the second functional unit; and the scoreboard is coupled to the second functional unit and to the second capture queue and configured to:
 store a second lifetime tracking value associated with an expected number of cycles to execute a second instruction using the second set of pipeline stages; 
 decrement the lifetime tracking value based on execution of the second instruction; 
 based on the interrupt, cause a state of the second set of pipeline stages that is associated with the second instruction to be stored in the second capture queue; and 
 based on completion of the interrupt and on the second lifetime tracking value: 
 cause the state of the second set of pipeline stages to be restored to the second set of pipeline stages; and 
 cause the execution of the second instruction using the second set of pipeline stages to be resumed. 
 
   
     
     
         9 . A circuit device comprising:
 a processor that includes:
 a functional unit that includes a set of pipeline stages; 
 a capture queue associated with the functional unit; 
 a scoreboard coupled to the functional unit and to the capture queue and configured to:
 store a lifetime tracking value associated with an expected number of cycles to execute an instruction using the set of pipeline stages; 
 decrement the lifetime tracking value based on execution of the instruction; 
 based on an exception event, cause a state of the set of pipeline stages that is associated with the instruction to be stored in the capture queue; and 
 based on completion of the exception event and on the lifetime tracking value: 
 cause the state to be restored to the set of pipeline stages; and 
 cause the execution of the instruction using the set of pipeline stages to be completed. 
 
   
     
     
         10 . The circuit device of  claim 9 , wherein the processor includes a vector data path that includes the functional unit. 
     
     
         11 . The circuit device of  claim 9 , wherein the processor includes a scalar data path that includes the functional unit. 
     
     
         12 . The circuit device of  claim 9 , wherein:
 the capture queue is a first capture queue;   the processor includes a second capture queue; and   the scoreboard is configured to:
 based on the exception event, cause the state of the set of pipeline stages to be stored in the second capture queue via the first capture queue; and 
 based on completion of the exception event, cause the state to be restored to the set of pipeline stages to be restored from the second capture queue via the first capture queue. 
   
     
     
         13 . The circuit device of  claim 12 , wherein the processor includes a cache memory that includes the second capture queue. 
     
     
         14 . A method comprising:
 receiving an instruction for execution using a set of pipeline stages;   based on the receiving of the instruction, determining a lifetime tracking value based on an expected number of cycles to execute the instruction;   executing the instruction using the set of pipeline stages;   during the executing of the instruction:
 decrementing the lifetime tracking value; 
 based on an interrupt, storing a state of the set of pipeline stages in a capture queue; and 
 based on completion of the interrupt and on the lifetime tracking value:
 restored the state to the set of pipeline stages; and 
 resume execution of the instruction using the set of pipeline stages. 
 
   
     
     
         15 . The method of  claim 14 , wherein the set of pipeline stages is associated with a vector data path. 
     
     
         16 . The method of  claim 14 , wherein the set of pipeline stages is associated with a scalar data path. 
     
     
         17 . The method of  claim 14 , wherein:
 the capture queue is a first capture queue;   the method comprises copying the state of the set of pipeline stages from the first capture queue to a second capture queue; and   the restoring of the state to the set of pipeline stages includes copying the state from the second capture queue to the set of pipeline stages via the first capture queue.   
     
     
         18 . The method of  claim 14  further comprising, during the executing of the instruction:
 stalling the set of pipeline stages; and 
 maintaining the lifetime tracking value based on the set of pipeline stages being stalled.