Microelectronic assemblies having conductive structures with different thicknesses

Abstract

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a dielectric layer, in a substrate, the dielectric layer including an electroless catalyst, wherein the electroless catalyst includes one or more of palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, and tantalum; a first conductive trace having a first thickness in the dielectric layer, wherein the first thickness is between 4 um and 143 um; and a second conductive trace having a second thickness in the dielectric layer, wherein the second thickness is between 2 um and 141 um, wherein the first thickness is greater than the second thickness, and wherein the first conductive trace and the second conductive trace have sloped sidewalls.

1 . A microelectronic assembly, comprising:
 a dielectric layer, in a substrate, including an electroless catalyst, wherein the electroless catalyst includes one or more of palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, and tantalum;   a first conductive trace having a first thickness in the dielectric layer, wherein the first thickness is between 4 um and 143 um; and   a second conductive trace having a second thickness in the dielectric layer, wherein the second thickness is between 2 um and 141 um, wherein the first thickness is greater than the second thickness, and wherein the first conductive trace and the second conductive trace have sloped sidewalls.   
     
     
         2 . The microelectronic assembly of  claim 1 , wherein the electroless catalyst in the dielectric layer has a weight percent of up to 10. 
     
     
         3 . The microelectronic assembly of  claim 1 , wherein the electroless catalyst in the dielectric layer is palladium having a weight percent of up to 5. 
     
     
         4 . The microelectronic assembly of  claim 1 , wherein the dielectric layer is doped by the electroless catalyst. 
     
     
         5 . The microelectronic assembly of  claim 1 , further comprising:
 a die electrically coupled to the substrate.   
     
     
         6 . The microelectronic assembly of  claim 5 , wherein the die is a central processing unit, a radio frequency chip, a power converter, or a network processor. 
     
     
         7 . The microelectronic assembly of  claim 1 , wherein the substrate is an interposer. 
     
     
         8 . A microelectronic assembly, comprising:
 a first conductive feature having a first thickness in a dielectric layer, of a substrate, the dielectric layer including an electroless catalyst, wherein the first thickness is between 4 um and 143 um; and   a second conductive feature having a second thickness in the dielectric layer of the substrate, wherein the second thickness is between 2 um and 141 um, wherein the second thickness is different from the first thickness, and wherein the first and second conductive features have sloped sidewalls.   
     
     
         9 . The microelectronic assembly of  claim 8 , wherein the electroless catalyst includes one or more of palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, or tantalum. 
     
     
         10 . The microelectronic assembly of  claim 8 , wherein the first and second conductive features are traces. 
     
     
         11 . The microelectronic assembly of  claim 8 , wherein the dielectric layer is doped by the electroless catalyst. 
     
     
         12 . The microelectronic assembly of  claim 8 , further comprising:
 a die electrically coupled to the substrate.   
     
     
         13 . The microelectronic assembly of  claim 12 , wherein the die is a central processing unit, a radio frequency chip, a power converter, or a network processor. 
     
     
         14 . The microelectronic assembly of  claim 12 , wherein the first conductive feature or the second conductive feature is electrically coupled to the die via conductive pathways in the substrate. 
     
     
         15 . A computing device, comprising:
 a package substrate having a first surface and an opposing second surface, the package substrate comprising:
 a dielectric layer including an electroless catalyst; 
 a first conductive trace having a first thickness in the dielectric layer, wherein the first thickness is between 4 um and 143 um; and 
 a second conductive trace having a second thickness in the dielectric layer, wherein the second thickness is between 2 um and 141 um, wherein the second thickness is different from the first thickness, and wherein the first conductive trace and the second conductive trace have sloped sidewalls; 
   a circuit board coupled to the first surface of the package substrate; and   a die coupled to the second surface of the package substrate.   
     
     
         16 . The computing device of  claim 15 , wherein the dielectric layer is doped by the electroless catalyst. 
     
     
         17 . The computing device of  claim 15 , wherein the electroless catalyst includes one or more of palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, or tantalum. 
     
     
         18 . The computing device of  claim 15 , wherein the computing device is a server device. 
     
     
         19 . The computing device of  claim 15 , wherein the computing device is a portable computing device. 
     
     
         20 . The computing device of  claim 15 , wherein the computing device is a wearable computing device.