Three-dimensional memory device and manufacturing method thereof

Abstract

A method for manufacturing a three-dimensional memory device includes forming a lower multi-layered stack by alternately stacking a plurality of first dielectric layers and a plurality of first sacrificial layers on a substrate; forming an etch stop layer on the lower multi-layered stack; forming an upper multi-layered stack by alternately stacking a plurality of second dielectric layers and a plurality of second sacrificial layers on the etch stop layer; forming a vertical trench by etching the upper multi-layered stack using the etch stop layer as an etch end target; removing the etch stop layer under the vertical trench; and forming a first stairway-shaped trench in the lower multi-layered stack under the vertical trench, and forming a second stairway-shaped trench in the upper multi-layered stack.

What is claimed is: 
     
         1 . A method for manufacturing a three-dimensional memory device, comprising:
 forming a lower multi-layered stack by alternately stacking a plurality of first dielectric layers and a plurality of first sacrificial layers on a substrate;   forming an etch stop layer on the lower multi-layered stack;   forming an upper multi-layered stack by alternately stacking a plurality of second dielectric layers and a plurality of second sacrificial layers on the etch stop layer;   forming a vertical trench by etching the upper multi-layered stack using the etch stop layer as an etch end target;   removing the etch stop layer under the vertical trench; and   forming a first stairway-shaped trench in the lower multi-layered stack under the vertical trench, and forming a second stairway-shaped trench in the upper multi-layered stack.   
     
     
         2 . The method according to  claim 1 , wherein the etch stop layer is formed of a material that has an etch selectivity different from the etch selectivity of the plurality of second dielectric layers and the plurality of second sacrificial layers. 
     
     
         3 . The method according to  claim 1 , wherein the etch stop layer includes at least one of polysilicon, tungsten and TiN. 
     
     
         4 . The method according to  claim 1 , further comprising, after the forming of the first and second stairway-shaped trenches, 
 replacing the plurality of first sacrificial layers and the plurality of second sacrificial layers with an electrode material.   
     
     
         5 . The method according to  claim 1 , further comprising, after the forming of the first and second stairway-shaped trenches, 
 replacing the plurality of first sacrificial layers, the plurality of second sacrificial layers and the etch stop layer with an electrode material.   
     
     
         6 . The method according to  claim 1 , wherein
 an uppermost layer of the lower multi-layered stack is a first sacrificial layer, and   the etch stop layer has a thickness that is thinner than the plurality of first sacrificial layers and the plurality of second sacrificial layers.   
     
     
         7 . The method according to  claim 1 , further comprising, before the forming of the upper multi-layered stack, 
 forming a lower channel hole that passes through the etch stop layer and the lower multi-layered stack.   
     
     
         8 . The method according to  claim 7 , further comprising, after the forming of the upper multi-layered stack,
 forming an upper channel hole, which communicates with the lower channel hole, by etching the upper multi-layered stack; and   forming a cell plug in the lower channel hole and the upper channel hole.   
     
     
         9 . A three-dimensional memory device comprising:
 a lower structure including a plurality of first dielectric layers and a plurality of first electrode layers that are alternately stacked on a substrate, and having an uppermost layer that is configured by one of the first electrode layers and has a thickness that is different from the thickness of an etch stop layer and the other underlying first electrode layers;   an upper structure including a plurality of second dielectric layers and a plurality of second electrode layers, which are alternately stacked on the lower structure;   a vertical trench exposing the lower structure by passing through the upper structure;   a first stairway-shaped trench, configured in the lower structure under the vertical trench, that communicates with the vertical trench; and   a second stairway-shaped trench configured in the upper structure.   
     
     
         10 . The three-dimensional memory device according to  claim 9 , wherein 
 a first electrode layer is configured immediately under the etch stop layer, and   the first electrode layer immediately under the etch stop layer configures a dummy word line.   
     
     
         11 . The three-dimensional memory device according to  claim 9 , wherein a first electrode layer, as an uppermost layer of the lower structure, configures a dummy word line. 
     
     
         12 . The three-dimensional memory device according to  claim 9 , further comprising:
 a lower channel hole extending to the substrate by passing through the lower structure;   an upper channel hole communicating with the lower channel hole by passing through the upper structure; and   a cell plug configured in the lower channel hole and the upper channel hole.   
     
     
         13 . A method for manufacturing a three-dimensional memory device, comprising:
 forming a lower multi-layered stack by alternately stacking a plurality of first dielectric layers and a plurality of first sacrificial layers on a substrate;   forming an etch stop layer on the lower multi-layered stack;   forming an upper multi-layered stack by alternately stacking a plurality of second dielectric layers and a plurality of second sacrificial layers on the etch stop layer;   forming a plurality of first vertical holes by etching the upper multi-layered stack using the etch stop layer as an etch end target;   removing the etch stop layer under the plurality of first vertical holes; and   forming a plurality of second vertical holes, which extend downward from the plurality of first vertical holes, in the lower multi-layered stack, and forming a plurality of third vertical holes in the upper multi-layered stack.   
     
     
         14 . The method according to  claim 13 , wherein the etch stop layer is formed of a material that has an etch selectivity different from the plurality of second dielectric layers and the plurality of second sacrificial layers. 
     
     
         15 . The method according to  claim 13 , wherein the etch stop layer includes at least one of polysilicon, tungsten and TiN. 
     
     
         16 . The method according to  claim 13 , further comprising, after the forming of the first, second and third vertical holes, 
 replacing the plurality of first sacrificial layers and the plurality of second sacrificial layers with an electrode material.   
     
     
         17 . The method according to  claim 13 , further comprising, after the forming of the first, second and third vertical holes, 
 replacing the plurality of first sacrificial layers, the plurality of second sacrificial layers and the etch stop layer with an electrode material.   
     
     
         18 . The method according to  claim 13 , wherein
 an uppermost layer of the lower multi-layered stack is a first sacrificial layer, and   the etch stop layer has a thickness that is thinner than the plurality of first sacrificial layers and the plurality of second sacrificial layers.