Substrate processing method

Abstract

Provided is a substrate processing method in which a liner layer is formed on the photo resist underlayer, followed by forming SiO2 patterning layer thereon. According to the embodiment, the liner layer is formed by providing a silicon-containing layer, followed by inert gas activated by providing a high frequency RF power and a low frequency RF power together simultaneously. Thus, a loss of photo resist underlayer may be minimized within the range that does not affect the device performance and the wet etch properties and the width between fine patterns may be kept constant while the thickness of the liner layer is thin.

What is claimed is: 
     
         1 . A substrate processing method, comprising,
 a first phase of forming a liner layer on a patterned structure; and   a second phase of forming a deposition layer on the liner layer;   wherein the first phase of forming a liner layer is carried out by providing a dual frequency RF power.   
     
     
         2 . The substrate processing method of  claim 1 , wherein,
 the first phase for forming the liner layer comprises,
 a first step of providing the substrate with a patterned structure to a reactor; 
 a second step of providing a first reactant to the substrate and forming a first source layer on the patterned structure; 
 a third step of providing a dual frequency RF power to the first source layer; 
 a fourth step of converting the first source layer into a second source layer; 
 wherein a third reactant is continuously provided throughout the second step to the fourth step. 
   
     
     
         3 . The substrate processing method of  claim 2 , wherein,
 the third step of providing a dual frequency RF power provides a low frequency RF power and a high frequency RF power simultaneously.   
     
     
         4 . The substrate processing method of  claim 3 , wherein,
 the low frequency of RF power ranges between 300 kHz to and 500 kHz; and   the high frequency of RF power ranges between 5 MHz and 60 MHz.   
     
     
         5 . The substrate processing method of  claim 2 , wherein,
 the first reactant comprises silicon, nitrogen, and carbon.   
     
     
         6 . The substrate processing method of  claim 5 , wherein, 
 the first reactant comprises at least one of TSA, (SiH 3 ) 3 N; DSO, (SiH 3 ) 2 ; DSMA, (SiH 3 ) 2 NMe; DSEA, (SiH 3 ) 2 NEt; DSIPA, (SiH 3 ) 2 N(iPr); DSTBA, (SiH 3 ) 2 N(tBu); DEAS, SiH 3 NEt 2 ; DTBAS, SiH 3 N(tBu) 2 ; BDEAS, SiH 2 (NEt 2 ) 2 ; BDMAS, SiH 2 (NMe 2 ) 2 ; BTBAS, SiH 2 (NHtBu) 2 ; BITS, SiH 2 (NHSiMe 3 ) 2 ; DIPAS, SiH 3 N(iPr) 2 ; TEOS, Si(OEt) 4 ; SiCl 4 ; HCD, Si 2 Cl 6 ; 3DMAS, SiH(N(Me) 2 ) 3 ; BEMAS, SiH 2 [N(Et)(Me)] 2 ; AHEAD, Si 2 (NHEt) 6 ; TEAS, Si(NHEt) 4 ; Si 3 Hs ; DCS, SiH 2 Cl 2 ; SiHl 3 ; SiH 2 l 2 ; or the mixture or derivatives thereof.   
     
     
         7 . The substrate processing method of  claim 2 , wherein,
 the first source layer is dissociated by the third reactant activated by the dual frequency RF power and is converted into the second source layer.   
     
     
         8 . The substrate processing method of  claim 7 , wherein
 the second source layer comprises: individual silicon elements, nitrogen element, carbon elements, or a mixture thereof.   
     
     
         9 . The substrate processing method of  claim 7 , wherein,
 the second source layer comprises a SiCN layer.   
     
     
         10 . The substrate processing method of  claim 2 , wherein,
 the third reactant comprises at least one of Ar, He, or N 2 , or the mixture thereof.   
     
     
         11 . The substrate processing method of  claim 1 , wherein,
 the second phase of forming the deposition layer on the liner layer comprises,
 a fifth step of providing a first reactant and forming a third source layer on the liner layer formed on the patterned structure; 
 a sixth step of providing a second reactant to the third source layer; 
 a seventh step of providing a high frequency RF power to the reactor and activating the second reactant; and 
 an eighth step for forming a compound by reacting the third source layer with the second reactant. 
   
     
     
         12 . The substrate processing method of  claim 11 , wherein,
 the third source layer is the same material as the first source layer.   
     
     
         13 . The substrate processing method of  claims 11 , wherein,
 the first reactant comprises at least one of TSA, (SiH 3 ) 3 N; DSO, (SiH 3 ) 2 ; DSMA, (SiH 3 ) 2 NMe; DSEA, (SiH 3 ) 2 NEt; DSIPA, (SiH 3 ) 2 N(iPr); DSTBA, (SiH 3 ) 2 N(tBu); DEAS, SiH 3 NEt 2 ; DTBAS, SiH 3 N(tBu) 2 ; BDEAS, SiH 2 (NEt 2 ) 2 ; BDMAS, SiH 2 (NMe 2 ) 2 ; BTBAS, SiH 2 (NHtBu) 2 ; BITS, SiH 2 (NHSiMe 3 ) 2 ; DIPAS, SiH 3 N(iPr) 2 ; TEOS, Si(OEt) 4 ; SiCl 4 ; HCD, Si 2 Cl 6 ; 3DMAS, SiH(N(Me) 2 ) 3 ; BEMAS, SiH 2 [N(Et)(Me)] 2 ; AHEAD, Si 2 (NHEt) 6 ; TEAS, Si(NHEt) 4 ; Si 3 Hs ; DCS, SiH 2 Cl 2 ; SiHl 3 ; SiH 2 l 2 ; or the mixture or derivatives thereof.   
     
     
         14 . The substrate processing method of  claim 11 , wherein,
 the second reactant comprises at least one of O 2 , O 3 , CO 2 , H 2 O, NO 2 , N 2 O, or the mixture thereof.   
     
     
         15 . The substrate processing method of  claim 11 , wherein,
 the second reactant comprises at least one of N2, N 2 O, NO 2 , NH3, N2H2, N2H4, or the mixture thereof.   
     
     
         16 . The substrate processing method of  claim 11 , wherein,
 the compound comprises at least one of silicon oxide or silicon nitride.   
     
     
         17 . The substrate processing method of  claim 11 , wherein,
 at least a part of the liner layer is converted into a compound by activated second reactant.   
     
     
         18 . The substrate processing method of  claim 17 , wherein,
 the whole liner layer is converted into a compound by activated second reactant.   
     
     
         19 . The substrate processing method of  claim 1 , wherein,
 the thickness of the liner layer is 10 Å or greater than 10 Å.   
     
     
         20 . The substrate processing method of  claim 11 , wherein,
 a loss of the patterned structure is below 5 Å.   
     
     
         21 . The substrate processing method of  claim 1 , wherein,
 the patterned structure comprises at least one of: a photo resist, carbon material, or amorphous silicon.   
     
     
         22 . The substrate processing method of  claim 11 , wherein,
 the widths of the patterned structures are almost the same.