Semiconductor memory device and manufacturing method thereof

Abstract

There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a source layer; a channel structure extending in a first direction from within the source layer; a source-channel contact layer surrounding the channel structure on the source layer; a first select gate layer overlapping with the source-channel contact layer and surrounding the channel structure; a stack including interlayer insulating layers and conductive patterns that are alternately stacked in the first direction and surrounding the channel structure, the stack overlapping with the first select gate layer; and a first insulating pattern that is formed thicker between the first select gate layer and the channel structure than between the stack and the channel structure.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a source layer;   a select gate layer including a metal layer overlapping with the source layer and a silicon layer interposed between the metal layer and the source layer, wherein the select gate layer is spaced apart from the source layer in a first direction;   a stack including interlayer insulating layers and conductive patterns that are alternately stacked in the first direction over the select gate layer;   a first channel structure and a second channel structure extending from the source layer in the first direction to penetrate the select gate layer and the stack;   an insulating pattern interposed between the select gate layer and each of the first and second channel structures and extending in the first direction to be interposed between the stack and each of the first and second channel structures;   a slit disposed between the first channel structure and the second channel structure and penetrating the silicon layer and the metal layer of the select gate layer, the interlayer insulating layers and the conductive patterns; and   a source-channel contact layer interposed between the silicon layer of the select gate layer and the source layer and being in contact with the source layer, wherein the source-channel contact layer surrounds the first channel structure and continuously extends to surround the second channel structure.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein the source layer includes an n-type doped silicon. 
     
     
         3 . The semiconductor memory device of  claim 1 , wherein the source-channel contact layer includes an n-type doped silicon. 
     
     
         4 . The semiconductor memory device of  claim 1 , wherein the source-channel contact layer includes a vertical portion extending into the slit, wherein the vertical portion is spaced apart from each of the select gate and the stack. 
     
     
         5 . The semiconductor memory device of  claim 1 , further comprising:
 a data storage layer disposed between the insulating pattern and each of the first channel structure and the second channel structure and disposed over the source-channel contact layer; and   a tunnel insulating layer disposed between the data storage layer and each of the first and second the channel structure over the source-channel contact layer.   
     
     
         6 . The semiconductor memory device of  claim 5 , wherein the source-channel contact layer protrudes toward the data storage layer and the tunnel insulating layer and is interposed between the insulating pattern and the silicon layer of the select gate layer. 
     
     
         7 . The semiconductor memory device of  claim 1 , wherein the insulating pattern includes:
 a first portion between the silicon layer of the select gate layer and each of the first channel structure and the second channel structure; and   a second portion disposed between the metal layer of the select gate layer and each of the first channel structure and the second channel structure and extending in the first direction to be interposed between the stack and each of the first channel structure and the second channel structure.   
     
     
         8 . The semiconductor memory device of  claim 7 , wherein the first portion of the insulating pattern is thicker than the second portion of the insulating pattern. 
     
     
         9 . The semiconductor memory device of  claim 1 , wherein the insulating pattern extends between the silicon layer of the select gate layer and the source-channel contact layer. 
     
     
         10 . The semiconductor memory device of  claim 1 , wherein the silicon layer of the select gate layer is spaced apart from each of the first channel structure and the second channel at a greater distance than the metal layer of the select gate layer.