Semiconductor memory device and method of fabricating the same

Abstract

A semiconductor memory device and a method for fabricating a semiconductor memory device, the device including a peripheral logic structure on a substrate; a horizontal conductive substrate on the peripheral logic structure; a stacked structure including a plurality of electrode pads stacked in a vertical direction; a plate contact plug connected to the horizontal conductive substrate; and a first penetration electrode connected to the lower connection wiring body, wherein upper surfaces of the plate contact plug and the first penetration electrode are on a same plane, the plate contact plug includes an upper part and a lower part directly connected to each other, the first penetration electrode includes an upper part and a lower part directly connected to each other, moving away from upper surfaces of the first penetration electrode and the plate contact plug, widths of the upper parts increase and widths of the lower parts decrease.

1 .- 32 . (canceled) 
     
     
         33 . A semiconductor memory device, comprising:
 a peripheral logic structure including a peripheral circuit and a lower connection wiring body on a substrate;   a horizontal conductive substrate extending along an upper surface of the peripheral logic structure;   a metallic plate film extending along a lower surface of the horizontal conductive substrate, the metallic plate film being between the lower connection wiring body and the horizontal conductive substrate;   a stacked structure including a plurality of electrode pads stacked in a vertical direction on the horizontal conductive substrate;   a plate contact plug connected to the horizontal conductive substrate and extending in the vertical direction; and   a penetration electrode connected to the lower connection wiring body and extending in the vertical direction,   wherein an upper surface of the plate contact plug and an upper surface of the penetration electrode are on a same plane.   
     
     
         34 . The semiconductor memory device as claimed in  claim 33 , wherein the metallic plate film is in contact with the horizontal conductive substrate. 
     
     
         35 . The semiconductor memory device as claimed in  claim 33 , wherein a part of the plate contact plug is in the horizontal conductive substrate. 
     
     
         36 . The semiconductor memory device as claimed in  claim 33 , wherein the plate contact plug penetrates the horizontal conductive substrate and is in contact with the metallic plate film. 
     
     
         37 . The semiconductor memory device as claimed in  claim 33 , wherein a plane at which the penetration electrode has a maximum width is at a same vertical level as a plane at which the plate contact plug has a maximum width, relative to an upper surface of the horizontal conductive substrate in the vertical direction. 
     
     
         38 . A method of fabricating a semiconductor memory device, the method comprising:
 forming a horizontal conductive substrate on a peripheral logic structure that includes a peripheral circuit and a lower connection wiring body;   forming a stacked structure including a plurality of stacked electrode pads in a vertical direction, and an interlayer insulation film covering the stacked structure, on the horizontal conductive substrate;   forming an electrode plug hole for exposing the plurality of stacked electrode pads, in the interlayer insulation film;   forming an insulating liner film along an upper surface of the interlayer insulation film and a profile of the electrode plug hole;   simultaneously forming a plate contact hole and a penetration electrode hole in the insulating liner film and the interlayer insulation film such that the plate contact hole exposes the horizontal conductive substrate and the penetration electrode hole exposes the lower connection wiring body; and   forming an electrode plug, a plate contact plug, and a penetration electrode that fill the electrode plug hole, the plate contact hole, and the penetration electrode hole, wherein a plane at which the penetration electrode hole has a maximum width is at a same vertical level as a plane at which the plate contact hole has a maximum width, relative to an upper surface of the horizontal conductive substrate in the vertical direction.   
     
     
         39 . The method of fabricating the semiconductor memory device as claimed in  claim 38 , further comprising removing at least a part of the insulating liner film from along the profile of the electrode plug hole prior to forming the electrode plug.