Memory devices and methods of manufacturing thereof

Abstract

A memory device includes a first transistor formed in a first region of a substrate. The first transistor includes a structure protruding from the substrate, and a first source/drain (S/D) structure coupled to a first end of the protruding structure. The memory device includes a second transistor formed in a second region of the substrate. The second transistor includes a number of first semiconductor layers that are vertically spaced apart from one another, a second S/D structure coupled to a first end of the first semiconductor layers; and a third S/D structure coupled to a second end of the first semiconductor layers. The first region and the second region are laterally separated from each other by an isolation structure.

What is claimed is: 
     
         1 . A one-time-programmable (OTP) memory device, comprising:
 a programming transistor formed in a first region of a substrate; and   a first reading transistor electrically coupled to the programming transistor in series and formed in a second region of the substrate, the first region being laterally separated from the second region by an isolation structure,   wherein the programming transistor includes a first gate structure straddling a structure protruding from the substrate, and the first reading transistor includes a second gate structure wrapping around each of a plurality of first nanostructures that are vertically spaced apart from one another.   
     
     
         2 . The OTP memory device of  claim 1 , wherein the protruding structure is configured as a channel of the programming transistor, and the plurality of nanostructures are collectively configured as a channel of the first reading transistor. 
     
     
         3 . The OTP memory device of  claim 1 , wherein the programming transistor includes a first source/drain (S/D) structure coupled to a first end of the protruded structure, and the first reading transistor includes a second S/D structure and a third S/D structures coupled to a first end and a second end of the plurality of first nanostructures, respectively. 
     
     
         4 . The OTP memory device of  claim 3 , wherein the first S/D structure and the second S/D structure are immediately adjacent to but separated from each other by the isolation structure. 
     
     
         5 . The OTP memory device of  claim 3 , wherein the first S/D structure has a first vertical height, and the second S/D structure and third S/D structure have a second vertical height, the second vertical height being greater than the first vertical height. 
     
     
         6 . The OTP memory device of  claim 3 , further comprising an interconnecting structure that is disposed above the substrate and connects the first S/D structure to at least one of the second S/D structure or the third S/D structure. 
     
     
         7 . The OTP memory device of  claim 1 , further comprising a second reading transistor electrically coupled to the first reading transistor in series and formed in the second region of the substrate, wherein the second reading transistor includes a third gate structure wrapping around each of a plurality of second nanostructures that are vertically spaced apart from one another. 
     
     
         8 . The OTP memory device of  claim 1 , further comprising at least one dummy gate structure disposed between the first region and the second region. 
     
     
         9 . A memory device, comprising:
 a substrate including a first region and a second region, wherein the first region and the second region are separated from each other with an isolation structure;   a first transistor formed in the first region; and   a second transistor formed in the second region and coupled to the first transistor in series through an interconnecting structure,   wherein the first transistor includes a first gate structure straddling a structure protruding from the substrate, and the second transistor includes a second gate structure wrapping around each of a plurality of first nanostructures that are vertically spaced apart from one another.   
     
     
         10 . The memory device of  claim 9 , wherein the first transistor and the second transistor collectively serve as a one-time-programmable (OTP) memory cell. 
     
     
         11 . The memory device of  claim 9 , wherein the protruding structure is configured as a channel of the first transistor, and the plurality of nanostructures are collectively configured as a channel of the second transistor. 
     
     
         12 . The memory device of  claim 9 , wherein the first transistor includes a first source/drain (S/D) structure coupled to a first end of the protruded structure, and the second transistor includes a second S/D structure and a third S/D structures coupled to a first end and a second end of the plurality of first nanostructures, respectively. 
     
     
         13 . The memory device of  claim 12 , wherein the first S/D structure and the second S/D structure are immediately adjacent to but separated from each other by the isolation structure. 
     
     
         14 . The memory device of  claim 12 , wherein the first S/D structure has a first vertical height, and the second S/D structure and third S/D structure have a second vertical height, the second vertical height being greater than the first vertical height. 
     
     
         15 . The memory device of  claim 12 , wherein the connecting structure connects the first S/D structure to one of the second S/D structure or the third S/D structure. 
     
     
         16 . The memory device of  claim 9 , further comprising a third transistor electrically coupled to the second transistor in series and formed in the second region of the substrate, wherein the third transistor includes a third gate structure wrapping around each of a plurality of second nanostructures that are vertically spaced apart from one another. 
     
     
         17 . The memory device of  claim 9 , further comprising at least one dummy gate structure disposed between the first region and the second region. 
     
     
         18 . A memory device, comprising:
 a substrate including a first region and a second region, wherein the first region and the second region are separated from each other with an isolation structure;   a first transistor formed in the first region and comprising:
 a first gate structure straddling a structure protruding from the substrate; 
 a first source/drain (S/D) structure coupled to a first end of the protruded structure; and 
   a second transistor formed in the second region, coupled to the first transistor in series through an interconnecting structure, and comprising:
 a second gate structure wrapping around each of a plurality of first nanostructures that are vertically spaced apart from one another; 
 a second S/D structure coupled to a first end of the plurality of first nanostructures; and 
 a third S/D structure coupled to a second end of the plurality of first nanostructures. 
   
     
     
         19 . The memory device of  claim 18 , wherein the first S/D structure has a first vertical height, and the second S/D structure and third S/D structure have a second vertical height, the second vertical height being greater than the first vertical height. 
     
     
         20 . The memory device of  claim 18 , wherein the connecting structure connects the first S/D structure to one of the second S/D structure or the third S/D structure.