Self-alignment of micro light emitting diode using planarization

Abstract

Embodiments relate to a method for fabricating a light-emitting-diode (LED). A metal layer is deposited on a p-type semiconductor. The p-type semiconductor is on an n-type semiconductor. The metal layer is patterned to define a p-metal. The p-type semiconductor is etched using the p-metal as an etch mask. Similarly, the n-type semiconductor is etched using the p-metal and the p-type semiconductor as an etch mask to define individual LEDs.

1 . A method of fabricating a light emitting diode (LED) device, comprising:
 forming a metal contact on a surface of a semiconductor stack comprising a p-type semiconductor and an n-type semiconductor;   etching the semiconductor stack to define the LED, wherein the metal contact is configured to selectively mask the semiconductor stack to pattern the semiconductor stack;   depositing a planarization layer over the LED;   etching the planarization layer to expose the metal contact, wherein the etching of the planarization layer and the etching of the semiconductor stack are both aligned to the metal contact.   
     
     
         2 . The method of  claim 1 , wherein the planarization layer is deposited over the metal contact used for selectively masking the etching of the semiconductor stack. 
     
     
         3 . The method of  claim 1 , wherein the deposited planarization layer has a first region disposed over the metal contact used for selectively masking the etching of the semiconductor stack, the first region having a first thickness, and a second region around the first region, the second region having a second thickness larger than the first thickness, and wherein etching the planarization layer comprises removing the first region to expose the metal contact, and etching the second region by at least the first thickness. 
     
     
         4 . The method of  claim 1 , wherein forming the metal contact on the surface of the semiconductor stack comprises:
 depositing a metal layer directly on a semiconductor stack; and   patterning the metal layer to define the metal contact.   
     
     
         5 . The method of  claim 1 , wherein the etching of the planarization layer and the etching of the semiconductor stack are both self-aligned to the metal contact. 
     
     
         6 . The method of  claim 1 , wherein the etching of the planarization layer is performed by at least a chemical-mechanical polishing (CMP) process followed by a dry-etching process on the planarization layer. 
     
     
         7 . The method of  claim 6 , wherein the dry-etching process is stopped when a thickness of the planarization layer is equal to or lower than a preset thickness. 
     
     
         8 . The method of  claim 6 , wherein the dry-etching process is stopped after the metal contact is exposed but before a top surface of the semiconductor stack is exposed. 
     
     
         9 . The method of  claim 1 , wherein etching the planarization layer to expose the metal contact comprises:
 planarizing the planarization layer; and   etching the planarized planarization layer to expose the metal contact without exposing a top surface of the semiconductor stack.   
     
     
         10 . A light emitting diode (LED) fabricated by a process comprising the steps of:
 forming a metal contact on a surface of a semiconductor stack comprising a p-type semiconductor and an n-type semiconductor;   etching the semiconductor stack to define the LED, wherein the metal contact is configured to selectively mask the semiconductor stack to pattern the semiconductor stack;   depositing a planarization layer over the LED;   etching the planarization layer to expose the metal contact, wherein the etching of the planarization layer and the etching of the semiconductor stack are both aligned to the metal contact.   
     
     
         11 . The LED of  claim 10 , wherein the planarization layer is deposited over the metal contact used for selectively masking the etching of the semiconductor stack. 
     
     
         12 . The LED of  claim 10 , wherein the deposited planarization layer has a first region disposed over the metal contact used for selectively masking the etching of the semiconductor stack, the first region having a first thickness, and a second region around the first region, the second region having a second thickness larger than the first thickness, and wherein etching the planarization layer comprises removing the first region to expose the metal contact, and etching the second region by at least the first thickness. 
     
     
         13 . The LED of  claim 10 , wherein forming the metal contact on the surface of the semiconductor stack comprises:
 depositing a metal layer directly on a semiconductor stack; and   patterning the metal layer to define the metal contact.   
     
     
         14 . The LED of  claim 10 , wherein the etching of the planarization layer and the etching of the semiconductor stack are both self-aligned to the metal contact. 
     
     
         15 . The LED of  claim 10 , wherein the etching of the planarization layer is performed by at least a chemical-mechanical polishing (CMP) process followed by a dry-etching process on the planarization layer. 
     
     
         16 . The LED of  claim 15 , wherein the dry-etching process is stopped when a thickness of the planarization layer is equal to or lower than a preset thickness. 
     
     
         17 . The LED of  claim 15 , wherein the dry-etching process is stopped after the metal contact is exposed but before a top surface of the semiconductor stack is exposed. 
     
     
         18 . The LED of  claim 10 , wherein etching the planarization layer to expose the metal contact comprises:
 planarizing the planarization layer; and   etching the planarized planarization layer to expose the metal contact without exposing a top surface of the semiconductor stack.   
     
     
         19 . A non-transitory computer readable storage medium configured to store instructions, the instructions, when executed by a fabrication tool, cause the fabrication tool to:
 forming a metal contact on a surface of a semiconductor stack comprising a p-type semiconductor and an n-type semiconductor;   etching the semiconductor stack to define the LED, wherein the metal contact is configured to selectively mask the semiconductor stack to pattern the semiconductor stack;   depositing a planarization layer over the LED;   etching the planarization layer to expose the metal contact, wherein the etching of the planarization layer and the etching of the semiconductor stack are both aligned to the metal contact.   
     
     
         20 . The non-transitory computer readable storage medium of  claim 19 , wherein the planarization layer is deposited over the metal contact used for selectively masking the etching of the semiconductor stack.