Nanosheet metal-oxide semiconductor field effect transistor with asymmetric threshold voltage

Abstract

A method of forming a semiconductor structure includes forming a nanosheet stack on a substrate. The nanosheet stack includes an alternating sequence of sacrificial nanosheets and channel nanosheets. The sacrificial nanosheets include second nanosheets located between first nanosheets and third nanosheets. The first nanosheets and the third nanosheets have a first germanium concentration that is lower than a second germanium concentration of the second nanosheets. The sacrificial nanosheets are selectively etched and the lower first germanium concentration causes the first nanosheets and the third nanosheets to be etched slower than the second nanosheets creating an indentation region on opposing sides of the nanosheet stack. The indentation region has a narrowing shape towards remaining second nanosheets of the sacrificial nanosheets.

What is claimed is: 
     
         1 . A method of forming a semiconductor structure, comprising:
 forming a nanosheet stack on a substrate, the nanosheet stack including an alternating sequence of sacrificial nanosheets and channel nanosheets, the sacrificial nanosheets including second nanosheets located between first nanosheets and third nanosheets, the first nanosheets and the third nanosheets having a first germanium concentration that is lower than a second germanium concentration of the second nanosheets; and   selectively etching the sacrificial nanosheets, wherein the lower first germanium concentration causes the first nanosheets and the third nanosheets to be etched slower than the second nanosheets creating an indentation region on opposing sides of the nanosheet stack, the indentation region having a narrowing shape towards remaining second nanosheets of the sacrificial nanosheets.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming a first inner spacer on opposing sides of the second nanosheets, the first inner spacer filling the indentation region;   selectively removing first portions of the first inner spacer located on a first side of the semiconductor structure to form first recesses, wherein second portions of the first inner spacer remain on a second side of the semiconductor structure opposing the second side; and   forming a second inner spacer on the opposing sides of the sacrificial nanosheets and in direct contact with the channel nanosheets, a first portion of the second inner spacer substantially filling the first recesses on the first side, the first portion of the second inner spacer on the first side having a protruding region extending from a middle top surface of the first portion of the second inner spacer towards remaining second layer of the sacrificial nanosheets.   
     
     
         3 . The method of  claim 2 , further comprising:
 forming a source region on the first side along sidewalls of the channel nanosheets and the second inner spacer and a drain region on the second side along opposing sidewalls of the channel nanosheets and the second inner spacer.   
     
     
         4 . The method of  claim 3 , further comprising:
 forming a dummy gate above the nanosheet stack adjacent to an offset spacer;   removing the dummy gate and the sacrificial nanosheets;   removing remaining portions of the first inner spacer from the second side, wherein removing the dummy gate, the sacrificial nanosheets and the remaining portions of the first inner spacer creates second recess; and   conformally depositing gate dielectrics and work function metals within the second recesses, the protruding region of the second inner spacer pinching off portions of the work function metals located on the first side to create an asymmetric work function metal distribution that increases threshold voltage on the first side.   
     
     
         5 . The method of  claim 4 , further comprising:
 forming a protective organic planarizing layer on the second side;   removing the first inner spacer from the first side; and   removing the protective organic planarizing layer from the second side.   
     
     
         6 . The method of  claim 1 , wherein the channel nanosheets comprise silicon and the first nanosheets, second nanosheets, and third nanosheets comprise silicon germanium, with the first germanium concentration of the first nanosheets and third nanosheets comprising 25% germanium, and the second germanium concentration of the second nanosheets comprising 35% germanium. 
     
     
         7 . The method of  claim 2 , wherein the second inner spacer is selected from the group consisting of SiN, SiC, SiOC, SiCN, BN, SiBN, SiBCN, SiOCN, and SiOxNy. 
     
     
         8 . The method of  claim 4 , wherein the protruding region provides a T-shaped inner spacer with a space between the protruding region and the channel nanosheets that is less than twice a thickness of a nitride layer of the work function metals. 
     
     
         9 . A method of forming a semiconductor structure, comprising:
 forming an inner spacer between channel nanosheets on a semiconductor substrate, a first portion of the inner spacer is located on a first side of the semiconductor structure and a second portion of the inner spacer is located on a second side of the semiconductor structure opposing the first side, the first portion of the inner spacer on the first side including a protruding region extending outwards from a middle top surface of the first portion of the inner spacer; and   forming a metal gate stack in direct contact with the inner spacer, the first portion of the inner spacer including the protruding region pinching off the metal gate stack for increasing a threshold voltage on the first side, the protruding region providing a T-shaped inner spacer with a space between the protruding region and the channel nanosheets being less than twice a thickness of an inner nitride layer in the metal gate stack.   
     
     
         10 . The method of  claim 9 , further comprising:
 forming a source region located on the first side and along sidewalls of the channel nanosheets separated from the metal gate stack by the first portion of the inner spacer; and   forming a drain region located on the second side and along opposing sidewalls of the channel nanosheets separated from the metal gate stack by the second portion of the inner spacer on the second side.   
     
     
         11 . The method of  claim 9 , further comprising:
 forming a metal gate above the metal gate stack adjacent to an offset spacer.   
     
     
         12 . The method of  claim 9 , wherein the semiconductor structure comprises an NFET device and the metal gate stack comprises a tri-layer gate metal stack formed by a doped transition metal layer located between an inner nitride layer and an outer nitride layer, the doped transition layer comprising an aluminum doped transition metal carbide. 
     
     
         13 . The method of  claim 12 , wherein the protruding region pinches off the inner nitride layer preventing deposition of the doped transition metal layer on the first side for increasing the threshold voltage. 
     
     
         14 . The method of  claim 12 , wherein the semiconductor structure comprises a PFET device and the metal gate stack comprises the inner nitride layer. 
     
     
         15 . The method of  claim 12 , wherein the protruding region pinches off the inner nitride layer decreasing an effective metal thickness of the inner nitride layer on the first side for increasing threshold voltage. 
     
     
         16 . The method of  claim 9 , wherein a material of the channel nanosheets comprises silicon and a material of the inner spacer is selected from the group consisting of SiN, SiC, SiOC, SiCN, BN, SiBN, SiBCN, SiOCN, and SiOxNy. 
     
     
         17 . A method of forming a semiconductor structure, comprising:
 forming a plurality of channel nanosheets above an isolation region on a semiconductor substrate;   forming an inner spacer between each of the plurality of channel nanosheets, a first portion of the inner spacer is located on a first side of the semiconductor structure, and a second portion of the inner spacer is located on a second side of the semiconductor structure opposing the first side, the first portion of the inner spacer on the first side including a protruding region extending outwards from a middle top surface of the first portion of the inner spacer; and   forming a metal gate stack separated from a source region located on the first side and along sidewalls of the plurality of channel nanosheets by the first portion of the inner spacer, the metal gate stack being separated from a drain region located on the second side and along opposing sidewalls of the plurality of channel nanosheets by the second portion of the inner spacer, the protruding region of the first portion of the inner spacer pinching off the metal gate stack for increasing a threshold voltage on the first side, the protruding region providing a T-shaped inner spacer with a space between the protruding region and the channel nanosheets being less than twice a thickness of an inner nitride layer in the metal gate stack.   
     
     
         18 . The method of  claim 17 , further comprising:
 forming a metal gate above the metal gate stack adjacent to an offset spacer.   
     
     
         19 . The method of  claim 17 , wherein the semiconductor structure comprises an NFET device and the metal gate stack comprises a tri-layer gate metal stack formed by a doped transition metal layer located between an inner nitride layer and an outer nitride layer, the doped transition layer comprising an aluminum doped transition metal carbide. 
     
     
         20 . The method of  claim 19 , wherein the protruding region pinches off the inner nitride layer preventing deposition of the doped transition metal layer on the first side for increasing the threshold voltage. 
     
     
         21 . The method of  claim 19 , wherein the semiconductor structure comprises a PFET device and the metal gate stack comprises the inner nitride layer. 
     
     
         22 . The method of  claim 19 , wherein the protruding region pinches off the inner nitride layer decreasing an effective metal thickness of the inner nitride layer on the first side for increasing the threshold voltage. 
     
     
         23 . The method of  claim 17 , wherein a material of the plurality of channel nanosheets comprises silicon and a material of the inner spacer is selected from the group consisting of SiN, SiC, SiOC, SiCN, BN, SiBN, SiBCN, SiOCN, and SiOxNy. 
     
     
         24 . A method of forming a semiconductor structure, comprising:
 forming a nanosheet stack above a substrate, the nanosheet stack including a channel nanosheet disposed between a stack of sacrificial nanosheets, the stack of sacrificial nanosheets including first sacrificial nanosheets disposed on opposite sides and in direct contact with the channel nanosheet, second sacrificial nanosheets in direct contact with a side of the first sacrificial nanosheets opposing a side of the second sacrificial nanosheets in contact with the channel nanosheets and third sacrificial nanosheets above and in direct contact with the second sacrificial nanosheets, wherein the first sacrificial nanosheets and the third sacrificial nanosheets have a first germanium concentration that is lower than a second germanium concentration of the second sacrificial nanosheets;   selectively etching the stack of sacrificial nanosheets to form an indentation region;   forming a first inner spacer partially filling the indentation region, the first inner spacer being located on opposite sides of the second sacrificial nanosheets and between the first and third sacrificial nanosheets;   selectively removing portions of the first and third sacrificial nanosheets;   selectively removing the first inner spacer from a first side of the nanosheet stack, the first inner spacer remaining on a second side of the nanosheet stack opposing the first side; and   depositing a second inner spacer on the first side of the nanosheet stack, wherein outer portions of the second inner spacer is aligned with the channel nanosheet.   
     
     
         25 . The method of  claim 24 , further comprising:
 conducting a replacement metal gate process on the semiconductor structure; and   removing the first inner spacer from the second side of the nanosheet stack before completing the replacement metal gate process.