Memory controller with skew compensated data transmit timing

Abstract

An integrated circuit device outputs a sequence of differently delayed calibration data timing signals to a DRAM component via a data-signal timing line as part of a timing calibration operation and then stores a delay value, based on at least one of the calibration data timing signals, that compensates for a difference in signal propagation times over the data-signal timing line and a command/address-signal timing line. After the timing calibration operation, the integrated circuit device outputs write data to the DRAM component and outputs a write data timing signal, delayed according to the delay value, to via the data-signal timing line to time reception of the first write data within the DRAM.

1 - 21 . (canceled) 
     
     
         22 . An integrated circuit device comprising:
 clock circuitry to output a clock signal to a dynamic random access memory device (DRAM) via a clock signal line; and   timing calibration circuitry operable during a timing calibration operation to:
 output a sequence of calibration data timing signals to the DRAM via a data timing signal line, the calibration data timing signals having respective phase offsets relative to the clock signal; 
 identify, as a write-data timing signal to be applied in subsequent memory write operations, one of the calibration data timing signals that yields, at the DRAM, a smaller timing skew relative to the clock signal than others of the calibration data timing signals. 
   
     
     
         23 . The integrated circuit device of  claim 22  wherein the timing calibration circuitry to identify the one of the calibration data timing signals that yields, at the DRAM, a smaller timing skew relative the clock signal than others of the calibration data timing signals comprises circuitry to select, as the write-data timing signal, one of the calibration data timing signals that arrives at the DRAM with less skew relative to arrival of the clock signal at the DRAM than all others of the calibration data timing signals. 
     
     
         24 . The integrated circuit device of  claim 22  wherein the timing calibration circuitry to output the sequence of calibration data timing signals having respective phase offsets relative to the clock signal comprises circuitry to:
 select, during each of a sequence of time intervals that transpires during the timing calibration operation, an output of a respective delay element within a chain of delay elements; and 
 transmit the output of the respective delay element onto the data timing signal line as a corresponding one of the calibration data timing signals. 
 
     
     
         25 . The integrated circuit device of  claim 22  wherein the timing calibration circuitry comprises circuitry to execute a sequence of dummy write operations as part of the timing calibration operation, including circuitry to output each of the calibration data timing signals to the DRAM as part of a respective one of the dummy write operations. 
     
     
         26 . The integrated circuit device of  claim 25  wherein the timing calibration circuitry further comprises circuitry to:
 execute memory read operations directed to the DRAM during the timing calibration operation, the memory read operations corresponding respectively to the dummy write operations; and 
 determine, through execution of the memory read operations, which calibration data timing signals within the sequence of calibration data timing signals enabled successful completion of the dummy write operations. 
 
     
     
         27 . The integrated circuit device of  claim 26  wherein the timing calibration circuitry to identify the one of the calibration data timing signals that yields, at the DRAM, a smaller timing skew relative to the clock signal than others of the calibration data timing signals comprises circuitry to identify the one of the calibration data timing signals based at least in part on the determination of which of the calibration data timing signals within the sequence of calibration data timing signals enabled successful completion of the dummy write operations. 
     
     
         28 . The integrated circuit device of  claim 22  further comprising circuitry to execute one of the memory write operations after completing the timing calibration operation, including write-data transmit circuitry to transmit write data to the DRAM via one or more data signal lines synchronously with respect to the write-data timing signal. 
     
     
         29 . The integrated circuit device of  claim 22  wherein the timing calibration circuitry to output the sequence of calibration data timing signals having respective phase offsets relative to the clock signal comprises circuitry to output a sequence of calibration data timing signals having respective phase offsets that collectively span an interval equal to or greater than a period of the clock signal. 
     
     
         30 . The integrated circuit device of  claim 22  wherein the timing calibration circuitry to output the sequence of calibration data timing signals having respective phase offsets relative to the clock signal comprises circuitry to output a sequence of calibration data timing signals having respective phase offsets staggered in time relative to one another by a predetermined fraction of a period of the clock signal. 
     
     
         31 . A method of operation within an integrated circuit device, the method comprising:
 outputting a clock signal to a dynamic random access memory device (DRAM) via a clock signal line;   outputting, during a timing calibration operation, a sequence of calibration data timing signals to the DRAM via a data timing signal line, the calibration data timing signals having respective phase offsets relative to the clock signal; and   identifying, as a write-data timing signal to be applied in subsequent memory write operations, one of the calibration data timing signals that yields, at the DRAM, a smaller timing skew relative to the clock signal than others of the calibration data timing signals.   
     
     
         32 . The method of  claim 31  wherein identifying the one of the calibration data timing signals that yields, at the DRAM, a smaller timing skew relative the clock signal than others of the calibration data timing signals comprises selecting, as the write-data timing signal, one of the calibration data timing signals that arrives at the DRAM with less skew relative to arrival of the clock signal at the DRAM than all others of the calibration data timing signals. 
     
     
         33 . The method of  claim 31  wherein outputting the sequence of calibration data timing signals having respective phase offsets relative to the clock signal comprises selecting, during each of a sequence of time intervals that transpires during the timing calibration operation, an output of a respective delay element within a chain of delay elements and transmitting the output of the respective delay element onto the data timing signal line as a corresponding one of the calibration data timing signals. 
     
     
         34 . The method of  claim 31  further comprising executing a sequence of dummy write operations as part of the timing calibration operation and wherein outputting the sequence of calibration data timing signals to the DRAM during the timing calibration operation comprises outputting each of the calibration data timing signals to the DRAM as part of a respective one of the dummy write operations. 
     
     
         35 . The method of  claim 34  further comprising determining, through execution of memory read operations directed to the DRAM during the timing calibration operation, which calibration data timing signals within the sequence of calibration data timing signals enabled successful completion of the dummy write operations. 
     
     
         36 . The method of  claim 35  wherein identifying the one of the calibration data timing signals that yields, at the DRAM, a smaller timing skew relative to the clock signal than others of the calibration data timing signals comprises identifying the one of the calibration data timing signals based at least in part on the determination of which of the calibration data timing signals within the sequence of calibration data timing signals enabled successful completion of the dummy write operations. 
     
     
         37 . The method of  claim 31  further comprising executing one of the memory write operations after completing the timing calibration operation, including transmitting write data to the DRAM via one or more data signal lines synchronously with respect to the write-data timing signal. 
     
     
         38 . The method of  claim 31  wherein outputting the sequence of calibration data timing signals having respective phase offsets relative to the clock signal comprises outputting a sequence of calibration data timing signals having respective phase offsets that collectively span an interval equal to or greater than a period of the clock signal. 
     
     
         39 . The method of  claim 31  wherein outputting the sequence of calibration data timing signals having respective phase offsets relative to the clock signal comprises outputting a sequence of calibration data timing signals having respective phase offsets staggered in time relative to one another by a predetermined fraction of a period of the clock signal. 
     
     
         40 . The method of  claim 31  wherein outputting the sequence of calibration data timing signals having respective phase offsets relative to the clock signal comprises outputting a sequence of data strobe signals. 
     
     
         41 . An integrated circuit device comprising:
 means for outputting a clock signal to a dynamic random access memory device (DRAM) via a clock signal line;   means for outputting, during a timing calibration operation, a sequence of calibration data timing signals to the DRAM via a data timing signal line, the calibration data timing signals having respective phase offsets relative to the clock signal; and   means for identifying, as a write-data timing signal to be applied in subsequent memory write operations, one of the calibration data timing signals that yields, at the DRAM, a smaller timing skew relative to the clock signal than others of the calibration data timing signals.