Method and Apparatus for Vector Based Finite Impulse Response (FIR) Filtering

Abstract

A method includes executing, by a processor a vector finite impulse response (VFIR) filter instruction that specifies coefficients, data elements, and a storage location. The executing includes reordering a subset of the data elements to provide each data element of the reordered subset of the data elements to a respective slice multiply component of a vector multiplier of the processor, generating, by the vector multiplier, filter outputs based on the coefficients and data elements, and storing the filter outputs in the storage location.

What is claimed is: 
     
         1 . A method comprising:
 executing, by a processor, a vector finite impulse response (VFIR) filter instruction that specifies coefficients, data elements, and a storage location, the executing including:
 reordering a subset of the data elements to provide each data element of the reordered subset of the data elements to a respective slice multiply component of a vector multiplier of the processor, generating, by the vector multiplier, filter outputs based on the coefficients and data elements, and storing the filter outputs in the storage location. 
   
     
     
         2 . The method of  claim 1 , wherein a number of the coefficients is four or eight. 
     
     
         3 . The method of  claim 2 , wherein a number of the data elements is twenty-three, and a number of the filter outputs is sixteen. 
     
     
         4 . The method of  claim 2 , wherein a number of the data elements is thirty-five, and a number of the filter outputs is thirty-two. 
     
     
         5 . The method of  claim 1 , wherein at least one of the data elements and the coefficients are signed. 
     
     
         6 . The method of  claim 1 , further comprising:
 storing the subset of the data elements before reordering the subset of the data elements.   
     
     
         7 . The method of  claim 1 , wherein the generating further comprises generating the filter outputs using the slice multiply components that are are disposed in a vector data path of the processor, wherein each slice multiply component is configured to receive a respective slice of the vector data path generate at least one respective filter output of the filter outputs. 
     
     
         8 . The method of  claim 6 , wherein the coefficients are duplicated such that all of the coefficients are provided to each slice multiply component of the slice multiplication components. 
     
     
         9 . The method of  claim 1 , wherein the data elements are provided by a streaming engine coupled to the processor. 
     
     
         10 . A processor comprising:
 a buffer configured to receive data elements;   permute networks coupled to the buffer; and   filter computation logic coupled to the permute networks;   wherein, in response to a vector finite impulse response (VFIR) filter instruction that specifies coefficients, data elements, and a storage location:
 at least one of the permute networks is configured to reorder a subset of the data elements to provide each data element of the reordered subset of the data elements to a respective slice multiply component of the filter computation logic; and 
 the filter computation logic is configured to generate filter outputs based on the coefficients and data elements; 
   wherein the processor is configured to store the filter outputs in the storage location.   
     
     
         11 . The processor of  claim 10 , wherein the at least one of the permute networks is for an n-tap filter in which the number of coefficients is n, in which n is 4 or 8. 
     
     
         12 . The processor of  claim 11 , wherein a number of the data elements is twenty-three and a number of the filter outputs is sixteen. 
     
     
         13 . The processor of  claim 11 , wherein a number of the data elements is thirty-five and a number of the filter outputs is thirty-two. 
     
     
         14 . The processor of  claim 10 , wherein the filter computation logic includes vector multiplication units disposed in a vector data path of the processor. 
     
     
         15 . A streaming engine interface, comprising:
 a buffer configured to receive data;   a permute component coupled to the buffer, the permute component including multiple permute networks, including a first permute network configured to operate on a vector finite impulse response (VFIR) filter instruction that specifies n coefficients and second permute network configured to operate on a VFIR filter instruction that specifies m coefficients, where n and m are different integers; and   filter computation logic coupled to the permute component;   wherein the first permute network is further configured to, in response to the VFIR filter instruction that specifies the n coefficients and also specifies data elements and a storage location, reorder a subset of the data elements to provide each data element of the reordered subset of the data elements to a respective slice multiply component of the filter computation logic,   wherein the filter computation logic is configured to generate filter outputs based on the n coefficients and data elements, and   wherein the processor is configured to store the filter outputs in the storage location.   
     
     
         16 . The streaming engine interface of  claim 15 , further comprising:
 combinatorial logic coupled between the permute component and the filter computation logic.   
     
     
         17 . The streaming engine interface of  claim 16 , wherein the combinatorial logic includes OR logic components. 
     
     
         18 . The streaming engine interface of  claim 15 , wherein the filter computation logic includes multiplication units. 
     
     
         19 . The streaming engine interface of  claim 15 , wherein the streaming engine interface is embodied in a digital signal processor (DSP). 
     
     
         20 . The streaming engine interface of  claim 15 , wherein the buffer is configured to receive data from a streaming engine.