Concurrent multi-bit adder

Abstract

A method for an associative memory device includes performing in parallel multi-bit operations of P pairs of multi-bit operands stored in columns of a memory array, each pair is stored in a different column, each bit i of each multi-bit operands of each pair is stored in a row of a section i in the column and each operation occurs in its associated column. A system includes a non-destructive associative memory array with multiple sections, each section j includes cells arranged in rows and columns, to store a bit j from a first multi-bit number in a first row and a bit j from a second multi-bit number in a second row of a same column, and a concurrent adder to, in parallel, perform per-section operations in each section, that includes one or more Boolean operations between a plurality of bits stored in rows of the section.

What is claimed is: 
     
         1 . A method for an associative memory device, the method comprising:
 in parallel, performing multi-bit operations of P pairs of multi-bit operands stored in columns of a memory array,   wherein each pair of said P pairs is stored in a different column of said array and each operation of said multi-bit operations occurs in its associated different column,   wherein each bit i of each of said multi-bit operands of each of said P pairs is stored in a row of a section i in said column.   
     
     
         2 . The method of  claim 1  wherein said each multi-bit operation of said multi-bit operations comprises a plurality of per-section operations, and wherein each per-section operation comprises one or more Boolean operations between a plurality of bits stored in said section. 
     
     
         3 . The method of  claim 2  wherein said performing comprises concurrently performing said per-section operations on a plurality of sections. 
     
     
         4 . The method of  claim 1  wherein said multi-bit operation is a multi-bit add operation. 
     
     
         5 . A system comprising:
 a non-destructive associative memory array comprising a plurality of sections, each section j comprising cells arranged in rows and columns, to store a bit j from a first multi-bit number in a first row and a bit j from a second multi-bit number in a second row of a same column; and   a concurrent adder to, in parallel perform per-section operations in each section, wherein each per-section operation comprises one or more Boolean operations between a plurality of bits stored in rows of said section.