Sram cell with balanced write port

Abstract

A semiconductor device includes first, second, third, fourth, and fifth active regions each extending lengthwise along a first direction, and first, second, third, fourth, fifth, and sixth gates each extending lengthwise along a second direction perpendicular to the first direction. The first, second, third, and fourth active regions comprise channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors. The first through sixth gates are configured to engage the channel regions of the first through sixth transistors respectively. The first, second, and fifth gates are electrically connected. The fifth active region is disposed between the second and third active regions.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 first, second, third, fourth, and fifth active regions each extending lengthwise along a first direction, wherein the first, second, third, and fourth active regions comprise channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors; and   first, second, third, fourth, fifth, and sixth gates each extending lengthwise along a second direction perpendicular to the first direction, wherein the first through sixth gates are configured to engage the channel regions of the first through sixth transistors respectively,   wherein:   the first, second, and fifth gates are electrically connected, and   the fifth active region is disposed between the second and third active regions.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first, second, and fifth gates are aligned on a straight line with the second gate between the first and fifth gates. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the third, fourth, and sixth gates are aligned on a straight line with the third gate between the fourth and sixth gates. 
     
     
         4 . The semiconductor device of  claim 1 , wherein one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, the third gate, and the fourth gate are electrically connected. 
     
     
         5 . The semiconductor device of  claim 1 , wherein one of the S/D regions of the third transistor, one of the S/D regions of the fourth transistor, and the fifth gate are electrically connected. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the first active region comprises a channel region and S/D regions of a seventh transistor, and the fourth active region comprises a channel region and S/D regions of an eighth transistor. 
     
     
         7 . The semiconductor device of  claim 6 , further comprising:
 a seventh gate configured to engage the channel region of the seventh transistor; and   an eighth gate configured to engage the channel region of the eighth transistor,   wherein:   the third, fourth, sixth, and seventh gates are aligned on a first straight line, and   the first, second, fifth, and eighth gates are aligned on a second straight line.   
     
     
         8 . The semiconductor device of  claim 1 , further comprising:
 a non-functional gate configured to engage an end portion of the second active region, wherein the non-functional gate and the sixth gate are aligned on a straight line.   
     
     
         9 . The semiconductor device of  claim 1 , further comprising:
 a conductive feature extending lengthwise along the second direction and electrically connected to one of the S/D regions of the second transistor,   wherein the conductive feature extends across the fifth active region.   
     
     
         10 . The semiconductor device of  claim 1 , wherein the first, fourth, fifth, and sixth transistors are of a first conductivity type, and the second and third transistors are of a second conductivity type opposite the first conductive type. 
     
     
         11 . A semiconductor device, comprising:
 first, second, third, and fourth transistors arranged in order from first to fourth along a first direction, wherein the first and fourth transistors are of a first conductivity type, the second and third transistors are of a second conductivity type opposite the first conductivity type, and each of the first through fourth transistors comprises a channel region, two source/drain (S/D) regions, and a gate stack over the respective channel region; and   fifth and sixth transistors between the second and third transistors, wherein the fifth and sixth transistors are of a same conductivity type, and each of the fifth and sixth transistors comprises a channel region, two source/drain (S/D) regions, and a gate stack over the respective channel region,   wherein the gate stacks of the first, second, and fifth transistors, one of the S/D regions of the third transistor, and one of the S/D regions of the fourth transistor are electrically connected.   
     
     
         12 . The semiconductor device of  claim 11 , wherein each of the first through sixth transistors is a FinFET. 
     
     
         13 . The semiconductor device of  claim 11 , wherein the gate stacks of the third and fourth transistors, one of the S/D regions of the first transistor, and one of the S/D regions of the second transistor are electrically connected. 
     
     
         14 . The semiconductor device of  claim 11 , wherein the gate stacks of the first, second, and fifth transistors share a common metal layer. 
     
     
         15 . The semiconductor device of  claim 11 , wherein the gate stacks of the third and fourth transistors share a common metal layer. 
     
     
         16 . The semiconductor device of  claim 11 , wherein the semiconductor device is a memory cell including a write port and a read port, the write port includes the first, second, third, and fourth transistors, and the read port includes the fifth, and sixth transistors. 
     
     
         17 . A memory cell, comprising:
 a first write port portion;   a second write port portion; and   a read port portion disposed between the first write port portion and the second write port portion,   wherein:   the first write port portion includes first, second, and seventh transistors,   the second write port portion includes third, fourth, and eighth transistors,   the read port portion includes fifth and sixth transistors, and   each of the first through eighth transistors include a channel region, two source/drain (S/D) regions, and a gate stack over the respective channel region.   
     
     
         18 . The memory cell of  claim 17 , further comprising:
 a conductive feature electrically connected to one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, the gate stack of the third transistor, and the gate stack of the fourth transistor.   
     
     
         19 . The memory cell of  claim 18 , wherein the conductive feature is disposed between the gate stack of the fifth transistor and the gate stack of the sixth transistor. 
     
     
         20 . The memory cell of  claim 17 , further comprising:
 a conductive feature electrically connected to one of the S/D regions of the third transistor, one of the S/D regions of the fourth transistor, the gate stack of the first transistor, the gate stack of the second transistor, and the gate stack of the fifth transistor.