Integrated ultralong time constant time measurement device and fabrication process

Abstract

An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunnelling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.

1 . A method for measuring a duration, comprising:
 charging a capacitive storage element;   discharging the charged capacitive storage element through a series connected plurality of elementary capacitive elements;   obtaining, on at least one node of the series connected plurality of elementary capacitive elements, a physical quantity that is representative of the discharging of the capacitive storage element; and   obtaining a duration of time that has elapsed between a start of an operation of discharging the capacitive storage element and a time at which the physical quantity is obtained.   
     
     
         2 . The method of  claim 1 , wherein each elementary capacitive element of the series connected plurality of elementary capacitive elements comprises:
 a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunnelling effect and a second conductive region,   wherein the first conductive region is housed in a trench extending from a front face of a semiconductor substrate into the substrate, and   wherein the dielectric layer rests on the front face of the semiconductor substrate and the second conductive region rests on the dielectric layer.   
     
     
         3 . The method of  claim 1 , wherein obtaining, on at least one node of the series connected plurality of elementary capacitive elements, the physical quantity comprises sensing voltage at said at least one node. 
     
     
         4 . The method of  claim 3 , wherein obtaining the duration of time comprises comparing the sensed voltage to a threshold and determining timing for a change in output logic state as a result said comparison of the sensed voltage to the threshold. 
     
     
         5 . The method of  claim 1 , wherein charging the capacitive storage element comprises capacitively coupling one node of the capacitive storage element to a supply potential and coupling another node of the capacitive storage element to ground. 
     
     
         6 . The method of  claim 5 , further comprising, after charging a capacitive storage element and before discharging the charged capacitive storage element, disconnecting the supply potential. 
     
     
         7 . A process for fabricating an integrated ultralong time constant time measurement device, comprising:
 forming trenches extending from a front face of a semiconductor substrate into the semiconductor substrate;   forming first conductive regions housed in said trenches;   forming dielectric layers resting on the front face, said dielectric layers having a thickness suited for allowing charge to flow by direct tunnelling effect;   forming second conductive regions resting on said dielectric layers; and   wherein respective stacks of a first conductive region, a dielectric layer and a second conductive region form a plurality of elementary capacitive elements connected in series.   
     
     
         8 . The process according to  claim 7 , further comprising forming a capacitive storage element that is connected to one end of the plurality of elementary capacitive elements connected in series. 
     
     
         9 . The process according to  claim 7 , wherein the dielectric layers and the second conductive regions are located facing respective portions of a width of said trenches housing the first conductive regions on said front face. 
     
     
         10 . The process according to  claim 7 , wherein pairs of elementary capacitive elements in said series are connected, alternately, by a second conductive region that is common to two consecutive elementary capacitive elements and by a first conductive region that is common to two consecutive elementary capacitive elements. 
     
     
         11 . The process according to  claim 7 , further comprising forming an electrical isolation region extending vertically into the semiconductor substrate from the first face, and wherein forming the trenches housing the first conductive regions comprises forming the trench to extend into and through the electrical isolation region. 
     
     
         12 . The process according to  claim 11 , further comprising lining each of the trenches with an insulating layer, wherein said insulating layer insulates the first conductive region from the semiconductor substrate located below the electrical isolation region. 
     
     
         13 . The method according to  claim 11 , wherein the electrical isolation region is a shallow trench isolation structure. 
     
     
         14 . The process according to  claim 7 , further comprising:
 forming a semiconductor well in the semiconductor substrate; and   forming a first contact and a second contact that are electrically connected by an electrical path comprising a section of the semiconductor well that is located between the bottom of a trench and the bottom of the semiconductor well.   
     
     
         15 . The process according to  claim 14 , further comprising providing a circuit connected to the first and second contacts and configured to detect an electrical discontinuity in the well between the first contact and the second contact.