Interface trap charge density reduction

Abstract

The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a first pair of fins and a second pair of fins disposed on a substrate;   an isolation feature disposed around and between the first pair of fins and second pair of fins;   a silicon nitride liner disposed between the isolation feature and surfaces of the first pair of fins as well as between and the isolation feature and surfaces of the second pair of fins;   a first source/drain feature disposed over source/drain regions of the first pair of fins; and   a second source/drain feature disposed over source/drain regions of the second pair of fins.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the isolation feature comprises silicon oxide or silicon oxynitride. 
     
     
         3 . The semiconductor structure of  claim 1 ,
 wherein the substrate comprises an n-type well and a p-type well,   wherein a composition of lower portions of the first pair of fins is the same as a composition of the n-type well, and   wherein a composition of lower portions of the second pair of fins is the same as a composition of the p-type well.   
     
     
         4 . The semiconductor structure of  claim 3 ,
 wherein top portions of the first pair of fins comprise silicon germanium,   wherein top portions of the second pair of fins comprise silicon.   
     
     
         5 . The semiconductor structure of  claim 4 , where a germanium content of the top portions of the first pair of fins is between about 20% and about 80%. 
     
     
         6 . The semiconductor structure of  claim 4 ,
 wherein the top portions of the first pair of fins are spaced apart from the lower portions of the first pair of fins by a semiconductor layer,   wherein the semiconductor layer comprises silicon.   
     
     
         7 . The semiconductor structure of  claim 4 , further comprising:
 a first silicon cap layer is disposed directly on sidewalls and top surfaces of the top portions of the first pair of fins in channel regions of the first pair of fins; and   a second silicon cap layer is disposed directly on sidewalls and top surfaces of the top portions of the second paid of fins in channel regions of the second pair of fins.   
     
     
         8 . The semiconductor structure of  claim 1 ,
 wherein the first source/drain feature comprises silicon germanium and a p-type dopant,   wherein the second source/drain feature comprises silicon and an n-type dopant.   
     
     
         9 . The semiconductor structure of  claim 1 , wherein the silicon nitride liner comprises a thickness between about 0.5 nm and about 3 nm. 
     
     
         10 . A semiconductor structure, comprising:
 a substrate;   a first fin disposed on the substrate and comprising:
 a first lower portion comprising silicon and an n-type dopant, 
 a middle portion over the first lower portion and comprising silicon, and 
 a first upper portion over the middle portion and comprising silicon germanium; 
   a second fin disposed on the substrate and comprising:
 a second lower portion comprising silicon and a p-type dopant, and 
 a second upper portion over the second lower portion and comprising silicon; 
   a dielectric liner along and in contact with sidewalls of the first lower portion of the first fin and the second lower portion of the second fin; and   a silicon cap layer over and in contact with a top surface of the first upper portion of the first fin, sidewalls of the first upper portion of the first fin, sidewalls of the middle portion of the first fin, a top surface of the second upper portion of the second fin, and sidewalls of the second upper portion of the second fin.   
     
     
         11 . The semiconductor structure of  claim 10 , wherein the dielectric liner comprises silicon nitride. 
     
     
         12 . The semiconductor structure of  claim 10 , further comprising:
 an isolation feature surround the first lower portion of the first fin and the second lower portion of the second fin,   wherein the isolation feature is spaced apart from the first lower portion and the second lower portion by the dielectric liner.   
     
     
         13 . The semiconductor structure of  claim 12 , wherein the isolation feature is spaced apart from the substrate by the dielectric liner. 
     
     
         14 . The semiconductor structure of  claim 10 , where a germanium content of the first upper portion of the first fin is between about 20% and about 80%. 
     
     
         15 . The semiconductor structure of  claim 10 , further comprising:
 an interfacial layer disposed over the silicon cap layer such that the interfacial layer is spaced apart from the first upper portion of the first fin and the second upper portion of the second fin by the silicon cap layer.   
     
     
         16 . The semiconductor structure of  claim 10 , wherein the first upper portion of the first fin and the second upper portion of the second fin are strained. 
     
     
         17 . A semiconductor structure, comprising:
 a first pair of fins and a second pair of fins disposed on a substrate;   an isolation feature disposed around and between the first pair of fins and second pair of fins;   a silicon nitride liner disposed between the isolation feature and surfaces of the first pair of fins as well as between and the isolation feature and surfaces of the second pair of fins;   a first source/drain feature disposed over the first pair of fins; and   a second source/drain feature disposed over the second pair of fins,   wherein the first pair of fins comprise silicon and an n-type dopant,   wherein the second pair of fins comprises silicon and a p-type dopant.   
     
     
         18 . The semiconductor structure of  claim 17 , wherein the silicon nitride liner comprises a thickness between about 0.5 nm and about 3 nm. 
     
     
         19 . The semiconductor structure of  claim 17 ,
 wherein the first source/drain feature comprises silicon germanium and a p-type dopant,   wherein the second source/drain feature comprises silicon and an n-type dopant.   
     
     
         20 . The semiconductor structure of  claim 17 ,
 wherein the first source/drain feature is in contact with top surfaces of the first pair of fins,   wherein the second source/drain feature is in contact with top surfaces of the second pair of fins.