Vector-by-matrix-multiplication array utilizing analog inputs

Abstract

Numerous examples are disclosed of an artificial neural network that comprises vector-by-matrix multiplication arrays utilizing analog inputs. In one example, a system comprises a vector by matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, a capacitor comprising a first terminal and a second terminal, the second terminal coupled to a common potential, a row decoder to enable an application of an input signal to the first terminal of the capacitor in response to an address, and a buffer coupled to the first terminal of the capacitor, the buffer to generate an output voltage for a respective row of the vector by matrix multiplication array.

What is claimed is: 
     
         1 . A system comprising:
 a vector by matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns;   a capacitor comprising a first terminal and a second terminal, the second terminal coupled to a common potential;   a row decoder to enable an application of an input signal to the first terminal of the capacitor in response to an address; and   a buffer coupled to the first terminal of the capacitor, the buffer to generate an output voltage for a respective row of the vector by matrix multiplication array.   
     
     
         2 . The system of  claim 1 ,
 wherein the row decoder enables the input signal by closing a switch with an output of the row decoder, wherein the switch, in a closed position, couples an input neuron current as the input signal to the first terminal of the capacitor; and   wherein the row decoder disables the input signal by opening the switch with the output of the row decoder, wherein the switch, in an open position, disconnects the input neuron current from the first terminal of the capacitor.   
     
     
         3 . The system of  claim 2 , wherein the input neuron current is received from a neural network array. 
     
     
         4 . The system of  claim 2 , wherein the input neuron current is a scaled current based on a current received from a neural network array. 
     
     
         5 . The system of  claim 2 , wherein the output voltage is generated according to a linear function performed on the input neuron current by the switch and the capacitor. 
     
     
         6 . The system of  claim 1 , wherein the plurality of non-volatile memory cells comprises stacked-gate flash memory cells. 
     
     
         7 . The system of  claim 1 , wherein the plurality of non-volatile memory cells comprises split-gate flash memory cells. 
     
     
         8 . A system comprising:
 a vector by matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns;   a switch to switchably couple a respective input to a respective row of the vector by matrix multiplication array; and   a row decoder for enabling the switch in response to an address so as to couple the respective input to the respective row of the vector by matrix multiplication array.   
     
     
         9 . The system of  claim 8 , wherein the respective input is received from a neural network array. 
     
     
         10 . The system of  claim 8 , wherein the respective input is applied to control gate terminals of non-volatile memory cells in the respective row. 
     
     
         11 . The system of  claim 8 , wherein the plurality of non-volatile memory cells comprises stacked-gate flash memory cells. 
     
     
         12 . The system of  claim 8 , wherein the plurality of non-volatile memory cells comprises split-gate flash memory cells. 
     
     
         13 . A method comprising:
 enabling, by a row decoder, the application of an input signal to a capacitor in response to an address;   generating, by a buffer, an output voltage using a voltage stored on the capacitor by the application; and   providing the output voltage to a row of non-volatile memory cells in a vector by matrix multiplication array.   
     
     
         14 . The method of  claim 13 , wherein the input signal is received from a neural network array. 
     
     
         15 . The method of  claim 13 , the output voltage is generated according to a linear function performed on the input signal. 
     
     
         16 . The method of  claim 13 , wherein the non-volatile memory cells comprise stacked-gate flash memory cells. 
     
     
         17 . The method of  claim 13 , wherein the non-volatile memory cells comprise split-gate flash memory cells.