Memory access gate

Abstract

Methods, systems, and devices for a memory access gate are described. A memory device may include a controller, memory dice, and a pad for receiving an externally provided control signal, such as a chip enable signal. The memory device may include a switching component for selecting the externally provided control signal or an internally generated control signal. The controller may provide the selected control signal to a memory die. The memory device may determine whether it is operating in a first mode or a second mode, and select the externally provided control signal or the internally generated control signal based on the determination. The first mode may be a diagnostic mode in some cases. The controller may include a secure register whose value may impact or control the switching. An authenticated host device may direct the controller to write the value to the secure register.

1 . (canceled) 
     
     
         2 . A method comprising:
 isolating a controller from a memory die;   coupling the controller with the memory die based at least in part on isolating the controller from the memory die;   receiving, from the controller, a signal for activating the memory die based at least in part on coupling the controller with the memory die; and   activating the memory die based at least in part on receiving the signal.   
     
     
         3 . The method of  claim 2 , wherein isolating the controller from the memory die comprises:
 isolating a first conductive path of the controller from an input of the memory die.   
     
     
         4 . The method of  claim 2 , wherein coupling the controller with the memory die comprises:
 coupling a second conductive path of the controller with an input of the memory die based at least in part on isolating the controller from the memory die.   
     
     
         5 . The method of  claim 4 , further comprising:
 writing a value to a register for selecting the second conductive path, wherein coupling the second conductive path is based at least in part on the value.   
     
     
         6 . The method of  claim 2 , further comprising:
 generating, by the controller, the signal for activating the memory die based at least in part on coupling the controller with the memory die.   
     
     
         7 . The method of  claim 2 , further comprising:
 selecting the signal for activating the memory die based at least in part on coupling the controller with the memory die; and   transmitting, to the memory die, the signal based at least in part on selecting the signal.   
     
     
         8 . The method of  claim 2 , further comprising:
 blocking one or more signals from being routed from one or more pads of the controller to the memory die based at least in part on transmitting the signal.   
     
     
         9 . The method of  claim 2 , further comprising:
 determining, at the controller, whether an electronic device comprising the controller and the memory die is operating in a first mode or a second mode, wherein isolating the controller from the memory die is based at least in part on determining that the electronic device is operating in the second mode.   
     
     
         10 . A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to:
 determine, at a controller of a memory device, that the memory device has entered a first mode associated with a performing a procedure;   couple a first conductive path of the controller with an input of a memory die of the memory device based at least in part on determining that the memory device has entered the first mode;   receive a signal for activating the memory die based at least in part on coupling the first conductive path of the controller with the input of the memory die; and   activate the memory die based at least in part on receiving the signal;   
     
     
         11 . The non-transitory computer-readable medium of  claim 10 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
 isolate a second conductive path of the controller from the input of the memory die based at least in part on determining that the memory device has entered the first mode, wherein receiving the signal is based at least in part on isolating the second conductive path.   
     
     
         12 . The non-transitory computer-readable medium of  claim 10 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
 perform the procedure associated with the first mode on the memory device based at least in part on activating the memory die.   
     
     
         13 . The non-transitory computer-readable medium of  claim 12 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
 output a result of the procedure to one or more pads of the controller based at least in part on performing the procedure.   
     
     
         14 . The non-transitory computer-readable medium of  claim 10 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
 block one or more signals from one or more pads of the controller from being routed to the memory die based at least in part on receiving the signal for activating the memory die.   
     
     
         15 . The non-transitory computer-readable medium of  claim 10 , wherein the signal is received via a pad of the controller coupled with the first conductive path. 
     
     
         16 . An apparatus, comprising:
 a memory die; and   a controller coupled with the memory die, the controller comprising:   a first conductive path for receiving a first signal for activating the memory die; and   a switching component coupled with the first conductive path and configured to couple the first conductive path with the memory die, wherein the controller is operable to direct the first signal to the memory die.   
     
     
         17 . The apparatus of  claim 16 , wherein the controller further comprises:
 a second conductive path for receiving a second signal for activating the memory die, wherein the controller is operable to direct the second signal to the memory die.   
     
     
         18 . The apparatus of  claim 17 , wherein the switching component is coupled with the second conductive path and configured to couple the second conductive path with the memory die. 
     
     
         19 . The apparatus of  claim 17 , wherein the switching component comprises:
 a first input coupled with the first conductive path; and   a second input coupled with the second conductive path.   
     
     
         20 . The apparatus of  claim 17 , further comprising:
 a register coupled with the switching component, wherein a value stored in the register indicates, to the switching component, whether to select the first conductive path or the second conductive path.   
     
     
         21 . The apparatus of  claim 16 , wherein the first conductive path couples a pad of the controller with the switching component.