Processing-in-memory (pim) system and operating methods of the pim system

Abstract

A processing-in-memory (PIM) controller includes a read/arithmetic queue logic circuit, a write queue logic circuit, and a scheduling logic circuit. The read/arithmetic queue logic circuit is configured to store a read queue and an arithmetic queue. The write queue logic circuit is configured to store a write queue for requesting to write data in the PIM device. The scheduling logic circuit is configured to perform the scheduling operation such that the write queue logic circuit outputs the arithmetic write queue before the read/arithmetic queue logic circuit outputs the arithmetic queue when the arithmetic queue exists in the read/arithmetic queue logic circuit and the arithmetic write queue exists in the write queue logic circuit.

What is claimed is: 
     
         1 . A processing-in-memory (PIM) controller configured to control a PIM device having a memory function and an arithmetic function, the PIM controller comprising:
 a read/arithmetic queue logic circuit configured to store a read queue and an arithmetic queue, the read queue being a request for reading data out of the PIM device, and the arithmetic queue being a request for arithmetic operation of the PIM device;   a write queue logic circuit configured to store a write queue for requesting to write data in the PIM device, the write queue including a memory write queue for storing data in the PIM device, and an arithmetic write queue for storing data necessary for the arithmetic operation performed in the PIM device; and   a scheduling logic circuit configured to perform a scheduling operation by adjusting an output sequence of the read queue, the arithmetic queue, and the write queue,   wherein the scheduling logic circuit is configured to perform the scheduling operation such that the write queue logic circuit outputs the arithmetic write queue before the read/arithmetic queue logic circuit outputs the arithmetic queue when the arithmetic queue exists in the read/arithmetic queue logic circuit and the arithmetic write queue exists in the write queue logic circuit.   
     
     
         2 . The PIM controller of  claim 1 ,
 wherein the read/arithmetic queue logic circuit includes a read/arithmetic queue storage region having a plurality of read/arithmetic queue entries, each of which stores the read queue or the arithmetic queue;   wherein the flag of a read/arithmetic queue entry in which the read queue is stored among the plurality of read/arithmetic queue entries is set to have a first binary number;   wherein the flag of the read/arithmetic queue entry in which the arithmetic queue is stored among the plurality of read/arithmetic queue entries is set to have a second binary number; and   wherein the scheduling logic circuit is configured to determine whether the arithmetic queue is exist in the read/arithmetic queue logic circuit based on a value of the flag of each of the plurality of read/arithmetic queue entries.   
     
     
         3 . The PIM controller of  claim 2 ,
 wherein the read/arithmetic queue logic circuit is configured to generate and transmit an arithmetic mode signal having a first level to the scheduling logic circuit when the arithmetic queue exists in the read/arithmetic queue logic circuit;   wherein the scheduling logic circuit is configured to generate and transmit an arithmetic mode enablement signal having the first level to the read/arithmetic queue logic circuit in response to receiving the arithmetic mode signal having the first level; and   wherein the read/arithmetic queue logic circuit is configured to output the arithmetic queue in response to receiving the arithmetic mode enablement signal having the first level.   
     
     
         4 . The PIM controller of  claim 3 ,
 wherein the read/arithmetic queue logic circuit is configured to generate and transmit the arithmetic mode signal having a second level to the scheduling logic circuit when the arithmetic queue is absent from the read/arithmetic queue logic circuit;   wherein the scheduling logic circuit is configured to generate and transmit the arithmetic mode enablement signal having the second level to the read/arithmetic queue logic circuit in response to receiving the arithmetic mode signal having the second level; and   wherein the read/arithmetic queue logic circuit is configured to output the read queue having an output priority in response to receiving the arithmetic mode enablement signal having the second level.   
     
     
         5 . The PIM controller of  claim 3 ,
 wherein each of the plurality of read/arithmetic queue entries further includes an index having information on validity and an output sequence of the read queue or the arithmetic queue stored therein,   wherein the read/arithmetic queue logic circuit includes:   a first arithmetic mode detector configured to receive the flag in each of the plurality of read/arithmetic queue entries to output the arithmetic mode signal;   a next read/arithmetic queue filter configured to receive the flag, the index, and the arithmetic mode enablement signal to generate and output a first arithmetic index signal;   a next read/arithmetic queue selector configured to receive an output signal of the next read/arithmetic queue filter and the index in each of the plurality of read/arithmetic queue entries to generate a read/arithmetic queue selection control signal; and   a read/arithmetic queue selection/output circuit configured to receive the read queues and the arithmetic queues from the read/arithmetic queue storage region to output one of the read queues and the arithmetic queues, which is selected by the read/arithmetic queue selection control signal.   
     
     
         6 . The PIM controller of  claim 5 ,
 wherein the first binary number and the second binary number are “0” corresponding to a logic “low(0)” level and “1” corresponding to a logic “high(1)” level, respectively; and   wherein the first arithmetic mode detector includes an OR gate for performing a logical OR operation of the flags of the read/arithmetic queue entries to output the result of the logical OR operation as the arithmetic mode signal.   
     
     
         7 . The PIM controller of  claim 5 , wherein the next read/arithmetic queue filter is configured to:
 output the index of the read/arithmetic queue entry storing the arithmetic queue as the first arithmetic index signal when the flag and the arithmetic mode enablement signal have a logic “high(1)” level; and   output the first arithmetic index signal having a logic “low(0)” level when at least one of the flag and the arithmetic mode enablement signal has a logic “low(0)” level.   
     
     
         8 . The PIM controller of  claim 5 , wherein the next read/arithmetic queue filter includes an AND gate for performing a logical AND operation of the flag, the index, and the arithmetic mode enablement signal and for outputting the result of the logical AND operation as the first arithmetic index signal. 
     
     
         9 . The PIM controller of  claim 5 , wherein the next read/arithmetic queue selector is configured to:
 generate the read/arithmetic queue selection control signal for selectively outputting the arithmetic queue stored in the read/arithmetic queue entry having the index designated by the first arithmetic index signal when the first arithmetic index signal is outputted from the next read/arithmetic queue filter; and   generate the read/arithmetic queue selection control signal for selectively outputting the read queue having an output priority according to the index when the first arithmetic index signal having a logic “low(0)” level is outputted from the next read/arithmetic queue filter.   
     
     
         10 . The PIM controller of  claim 5 , wherein the read/arithmetic queue logic circuit further includes a first counter to count the total number of the read queues and the arithmetic queues stored in the read/arithmetic queue storage region to generate a first queue counted value. 
     
     
         11 . The PIM controller of  claim 10 , wherein the first counter is suitable for:
 performing a first operation that increases the first queue counted value by one to transmit the increased value of the first queue counted value to the scheduling logic circuit when the read queue or the arithmetic queue is stored in the read/arithmetic queue logic circuit; and   performing a second operation that decreases the first queue counted value by one to transmit the decreased value of the first queue counted value to the scheduling logic circuit when the read queue or the arithmetic queue is outputted from the read/arithmetic queue logic circuit.   
     
     
         12 . The PIM controller of  claim 11 ,
 wherein the first operation is performed in response to a first queue input control signal outputted from the scheduling logic circuit; and   wherein the second operation is performed in response to a first queue output control signal outputted from the scheduling logic circuit.   
     
     
         13 . The PIM controller of  claim 1 ,
 wherein the write queue logic circuit includes a write queue storage region having a plurality of write queue entries, each of which stores the memory write queue or the arithmetic write queue;   wherein the flag of a certain write queue entry of the plurality of write queue entries is set to have a first binary number when the memory write queue is stored in the certain write queue entry;   wherein the flag of the certain write queue entry of the plurality of write queue entries is set to have a second binary number when the arithmetic write queue is stored in the certain write queue entry; and   wherein the scheduling logic circuit is configured to determine whether the arithmetic write queue is exist in the write queue logic circuit based on a value of the flag of each of the plurality of write queue entries.   
     
     
         14 . The PIM controller of  claim 13 ,
 wherein the write queue logic circuit is configured to generate and transmit an arithmetic write mode signal having a first level to the scheduling logic circuit when the arithmetic write queue exists in the plurality of write queue entries;   wherein the scheduling logic circuit is configured to generate and transmit an arithmetic write mode enablement signal having the first level to the write queue logic circuit in response to receiving the arithmetic write mode signal having the first level; and   wherein the write queue logic circuit is configured to output the arithmetic write queue in response to receiving the arithmetic write mode enablement signal having the first level.   
     
     
         15 . The PIM controller of  claim 14 ,
 wherein the write queue logic circuit is configured to generate and transmit the arithmetic write signal having a second level to the scheduling logic circuit when the arithmetic write queue is absent from the write queue logic circuit;   wherein the scheduling logic circuit is configured to generate and transmit the arithmetic write enablement signal having the second level to the write queue logic circuit in response to receiving the arithmetic write signal having the second level; and   wherein the write queue logic circuit is configured to output the memory write queue having an output priority in response to receiving the arithmetic write enablement signal having the second level.   
     
     
         16 . The PIM controller of  claim 14 ,
 wherein each of the plurality of write queue entries further includes an index having information on validity and an output sequence of the memory write queue or the arithmetic write queue stored therein; and   wherein the write queue logic circuit includes:   a second arithmetic mode detector configured to receive the flags of the plurality of write queue entries to output the arithmetic write signal;   a next write queue filter configured to receive the flag, the index, and the arithmetic mode enablement signal to generate and output a second arithmetic index signal;   a next write queue selector configured to receive an output signal of the next write queue filter and the indexes of the plurality of write queue entries to generate a write queue selection control signal; and   a write queue selection/output circuit configured to receive the memory write queues and the arithmetic write queues from the write queue storage region to output one of the memory write queues and the arithmetic write queues, which is selected by the write queue selection control signal.   
     
     
         17 . The PIM controller of  claim 16 ,
 wherein the first binary number and the second binary number are “0” corresponding to a logic “low(0)” level and “1” corresponding to a logic “high(1)” level, respectively; and   wherein the second arithmetic mode detector includes an OR gate for performing a logical OR operation of the flags of the write queue entries to output the result of the logical OR operation as the arithmetic write signal.   
     
     
         18 . The PIM controller of  claim 16 , wherein the next write queue filter is configured to:
 output the index of the write queue entry storing the arithmetic write queue as the second arithmetic index signal when the flag and the arithmetic write enablement signal have a logic “high(1)” level; and   output the second arithmetic index signal having a logic “low(0)” level when at least one of the flag and the arithmetic write enablement signal has a logic “low(0)” level.   
     
     
         19 . The PIM controller of  claim 16 , wherein the next write queue filter includes an AND gate for performing a logical AND operation of the flag, the index, and the arithmetic write enablement signal and outputting the result of the logical AND operation as the second arithmetic index signal. 
     
     
         20 . The PIM controller of  claim 16 , wherein the next write queue selector is configured to:
 generate the write queue selection control signal for selectively outputting the arithmetic write queue stored in the write queue entry having the index designated by the second arithmetic index signal when the second arithmetic index signal is outputted from the next write queue filter; and   generate the write queue selection control signal for selectively outputting the memory write queue having an output priority according to the index when the second arithmetic index signal having a logic “low(0)” level is outputted from the next write queue filter.   
     
     
         21 . The PIM controller of  claim 16 , wherein the write queue logic circuit further includes a second counter to count the total number of the memory write queues and the arithmetic write queues stored in the write queue storage region to generate a second queue counted value. 
     
     
         22 . The PIM controller of  claim 21 , wherein the second counter is suitable for:
 performing a third operation that increases the second queue counted value by one to transmit the increased value of the first queue counted value to the scheduling logic circuit when the memory write queue or the arithmetic write queue is stored in the write queue logic circuit; and   performing a fourth operation that decreases the second queue counted value by one to transmit the decreased value of the second queue counted value to the scheduling logic circuit when the memory write queue or the arithmetic write queue is outputted from the write queue logic circuit.   
     
     
         23 . The PIM controller of  claim 22 ,
 wherein the third operation is performed in response to a second queue input control signal outputted from the scheduling logic circuit; and   wherein the fourth operation is performed in response to a second queue output control signal outputted from the scheduling logic circuit.   
     
     
         24 . The PIM controller of  claim 1 ,
 wherein the scheduling logic circuit performs the scheduling operation such that the arithmetic write queue, the arithmetic queue, and the read queue are sequentially outputted when the arithmetic queue exists in the read/arithmetic queue logic circuit and the arithmetic write queue exists in the write queue logic circuit;   wherein the scheduling logic circuit performs the scheduling operation such that the arithmetic queue, the read queue, and the write queue are sequentially outputted when the arithmetic queue exists in the read/arithmetic queue logic circuit and the arithmetic write queue is absent from the write queue logic circuit; and   wherein the scheduling logic circuit performs the scheduling operation such that the read queue and the write queue are sequentially outputted when the arithmetic queue is absent from the read/arithmetic queue logic circuit.   
     
     
         25 . The PIM controller of  claim 1 ,
 wherein the scheduling logic circuit performs the scheduling operation such that the read queue and the write queue are sequentially outputted when the arithmetic queue is absent from the read/arithmetic queue logic circuit; and   wherein the scheduling logic circuit performs the scheduling operation such that the write queue has an output priority over the read queue until the number of the write queues stored in the write queue logic circuit becomes less than a maximum threshold value when the number of the write queues stored in the write queue logic circuit is equal to or greater than the maximum threshold value.   
     
     
         26 . The PIM controller of  claim 1 , wherein when an address of the read queue transmitted to the read/arithmetic queue logic circuit is the same as an address of the write queue stored in the write queue logic circuit, data of the write queue stored in the write queue logic circuit are transmitted to a host and the read queue transmitted to the read/arithmetic queue logic circuit is not stored in the read/arithmetic queue logic circuit.