Bandgap current reference

Abstract

A bandgap current reference circuit includes a bandgap core circuit and an error amplifier. The bandgap core circuit is configured to generate a zero temperature coefficient bandgap current. The bandgap core circuit includes a bipolar transistor. The bipolar transistor is configured to pass a current that is proportional to absolute temperature (PTAT current). The error amplifier is coupled to the bandgap core circuit and includes a bipolar differential input pair. The bipolar differential input pair is configured to ensure that the PTAT current is flowing in the bipolar transistor.

What is claimed is: 
     
         1 . A circuit, comprising:
 a bandgap circuit; and   an error amplifier circuit coupled to the bandgap circuit, the error amplifier circuit including:
 a gain stage circuit; and 
 a differential input stage circuit coupled to the gain stage circuit, the differential input stage circuit including:
 a first transistor including a control terminal, a first terminal, and a second terminal; 
 a second transistor including a control terminal, a first terminal, and a second terminal, wherein the second terminal of the second transistor is coupled to the second terminal of the first transistor; 
 a third transistor including a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is coupled to the control terminal of the second transistor, and the first terminal of the third transistor is coupled to the first terminal of the first transistor; and 
 a fourth transistor including a control terminal, a first terminal, and a second terminal, wherein the second terminal of the third transistor is coupled to the second terminal of the fourth transistor, the control terminal of the fourth transistor is coupled to the bandgap circuit, and the first terminal of the fourth transistor is coupled to the first terminal of the second transistor. 
 
   
     
     
         2 . The circuit of  claim 1 , wherein:
 the bandgap circuit includes:
 a fifth transistor including a control terminal, a first terminal, and a second terminal; 
 a sixth transistor including a control terminal, a first terminal, and a second terminal, wherein the control terminal of the sixth transistor is coupled to the first terminal of the fifth transistor; 
 a first resistor coupled between the second terminal of the fifth transistor and a ground terminal; 
 a second resistor coupled between the first terminal of the fifth transistor and the ground terminal; and 
 a third resistor coupled between the first terminal of the sixth transistor and the ground terminal. 
   
     
     
         3 . The circuit of  claim 2 , wherein:
 the control terminal of the second transistor and the control terminal of the third transistor are coupled to the first terminal of the sixth transistor;   the control terminal of the first transistor is coupled to the ground terminal; and   the control terminal of the fourth transistor is coupled to the control terminal of the second transistor.   
     
     
         4 . The circuit of  claim 1 , wherein:
 the second terminal of the first transistor is a first emitter and the second terminal of the second transistor is a second emitter; and   the second emitter is larger than the first emitter.   
     
     
         5 . The circuit of  claim 1 , wherein:
 the error amplifier circuit includes a gain stage circuit including a first input terminal and a second input terminal;   the first terminal of the first transistor and the first terminal of the third transistor are coupled to a first input terminal of the gain stage circuit; and   the first terminal of the second transistor and the first terminal of the fourth transistor are coupled to a second input terminal of the gain stage circuit.   
     
     
         6 . The circuit of  claim 5 , wherein:
 the gain stage circuit includes:
 a seventh transistor including a control terminal, a first terminal, and a second terminal; 
 an eighth transistor including a control terminal, a first terminal coupled to the first terminal of the seventh transistor, and a second terminal; 
 a ninth transistor including a control terminal, a first terminal coupled to the second terminal of the eighth transistor and the first input terminal of the gain stage circuit, and a second terminal coupled to a ground terminal; 
 a tenth transistor including a control terminal coupled to the control terminal of the seventh transistor, a first terminal coupled to the control terminal of the tenth transistor, and a second terminal coupled to the second terminal of the seventh transistor; 
 an eleventh transistor including a control terminal coupled to the control terminal of the eighth transistor, a first terminal coupled to the first terminal of the tenth transistor, and a second terminal coupled to the second input terminal of the gain stage circuit; and 
 a twelfth transistor including a control terminal coupled to the control terminal of the ninth transistor, a first terminal coupled to the second terminal of the eleventh transistor and the second input terminal of the gain stage circuit, and a second terminal coupled to the second terminal of the ninth transistor and to the ground terminal. 
   
     
     
         7 . The circuit of  claim 1 , wherein:
 the error amplifier circuit includes a first current source coupled to the second terminal of the first transistor and the second terminal of the second transistor; and   the error amplifier circuit includes a second current source coupled to the second terminal of the third transistor and the second terminal of the fourth transistor.   
     
     
         8 . The circuit of  claim 1 , wherein:
 the first transistor is a first bipolar junction transistor;   the second transistor is a second bipolar junction transistor;   the third transistor is a first field effect transistor; and   the fourth transistor is a second field effect transistor.   
     
     
         9 . A circuit, comprising:
 a bandgap circuit; and   an error amplifier circuit coupled to the bandgap circuit, the error amplifier circuit including:
 a gain stage circuit; and 
 a differential input stage circuit coupled to the gain stage circuit, the differential input stage circuit including:
 a first differential input pair of transistors; and 
 a second differential input pair of transistors. 
 
   
     
     
         10 . The circuit of  claim 9 , wherein:
 the first differential input pair of transistors includes:
 a first transistor including a control terminal, a first terminal, and a second terminal; 
 a second transistor including a control terminal, a first terminal, and a second terminal, wherein the second terminal of the second transistor is coupled to the second terminal of the first transistor; and 
   the second differential input pair of transistors includes:
 a third transistor including a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is coupled to the control terminal of the second transistor, and the first terminal of the third transistor is coupled to the first terminal of the first transistor; and 
 a fourth transistor including a control terminal, a first terminal, and a second terminal, wherein the second terminal of the third transistor is coupled to the second terminal of the fourth transistor, the control terminal of the fourth transistor is coupled to the bandgap circuit, and the first terminal of the fourth transistor is coupled to the first terminal of the second transistor. 
   
     
     
         11 . The circuit of  claim 10 , wherein:
 the bandgap circuit includes:
 a fifth transistor including a control terminal, a first terminal, and a second terminal; 
 a sixth transistor including a control terminal, a first terminal, and a second terminal, wherein the control terminal of the sixth transistor is coupled to the first terminal of the fifth transistor; 
 a first resistor coupled between the second terminal of the fifth transistor and a ground terminal; 
 a second resistor coupled between the first terminal of the fifth transistor and the ground terminal; and 
 a third resistor coupled between the first terminal of the sixth transistor and the ground terminal. 
   
     
     
         12 . The circuit of  claim 11 , wherein:
 the control terminal of the second transistor and the control terminal of the third transistor are coupled to the first terminal of the sixth transistor;   the control terminal of the first transistor is coupled to the ground terminal; and   the control terminal of the fourth transistor is coupled to the control terminal of the second transistor.   
     
     
         13 . The circuit of  claim 10 , wherein:
 the second terminal of the first transistor is a first emitter and the second terminal of the second transistor is a second emitter; and   the second emitter is larger than the first emitter.   
     
     
         14 . The circuit of  claim 10 , wherein:
 the error amplifier circuit includes a gain stage circuit including a first input terminal and a second input terminal;   the first terminal of the first transistor and the first terminal of the third transistor are coupled to a first input terminal of the gain stage circuit; and   the first terminal of the second transistor and the first terminal of the fourth transistor are coupled to a second input terminal of the gain stage circuit.   
     
     
         15 . The circuit of  claim 14 , wherein:
 the gain stage circuit includes:
 a seventh transistor including a control terminal, a first terminal, and a second terminal; 
 an eighth transistor including a control terminal, a first terminal coupled to the first terminal of the seventh transistor, and a second terminal; 
 a ninth transistor including a control terminal, a first terminal coupled to the second terminal of the eighth transistor and the first input terminal of the gain stage circuit, and a second terminal coupled to a ground terminal; 
 a tenth transistor including a control terminal coupled to the control terminal of the seventh transistor, a first terminal coupled to the control terminal of the tenth transistor, and a second terminal coupled to the second terminal of the seventh transistor; 
 an eleventh transistor including a control terminal coupled to the control terminal of the eighth transistor, a first terminal coupled to the first terminal of the tenth transistor, and a second terminal coupled to the second input terminal of the gain stage circuit; and 
 a twelfth transistor including a control terminal coupled to the control terminal of the ninth transistor, a first terminal coupled to the second terminal of the eleventh transistor and the second input terminal of the gain stage circuit, and a second terminal coupled to the second terminal of the ninth transistor and to the ground terminal. 
   
     
     
         16 . The circuit of  claim 10 , wherein:
 the error amplifier circuit includes a first current source coupled to the second terminal of the first transistor and the second terminal of the second transistor; and   the error amplifier circuit includes a second current source coupled to the second terminal of the third transistor and the second terminal of the fourth transistor.   
     
     
         17 . The circuit of  claim 10 , wherein:
 the first transistor is a first bipolar junction transistor;   the second transistor is a second bipolar junction transistor;   the third transistor is a first field effect transistor; and   the fourth transistor is a second field effect transistor.   
     
     
         18 . A data acquisition system, comprising:
 a processor;   a voltage regulator coupled to the processor, the voltage regulator including:
 a bandgap circuit; and 
 an error amplifier circuit coupled to the bandgap circuit, the error amplifier circuit including:
 a first differential input pair of transistors; and 
 a second differential input pair of transistors. 
 
   
     
     
         19 . The data acquisition system of  claim 18 , wherein:
 the bandgap circuit is configured to generate a zero-temperature coefficient bandgap current; and   the bandgap circuit includes a bipolar transistor configured to pass a current that is proportional to absolute temperature (a PTAT current).   
     
     
         20 . The data acquisition system of  claim 18 , wherein:
 the first differential input pair of transistors are active during steady-state operation.