Co-optimization of memory and logic devices by source/drain modulation and structures thereof

Abstract

Methods and structures for the co-optimization of memory and logic devices. A device includes a substrate having a first region and a second region. The device may include a first gate structure disposed in the first region and a second gate structure disposed in the second region. The device may further include a first source/drain feature disposed adjacent to the first gate structure and a second source/drain feature disposed adjacent to the second gate structure. A first top surface of the first source/drain feature and a second top surface of the second source/drain feature are substantially level. A first bottom surface of the first source/drain feature is a first distance away from the first top surface, and a second bottom surface of the second source/drain feature is a second distance away from the second top surface. In some cases, the second distance is greater than the first distance.

What is claimed is: 
     
         1 . A method of fabricating a semiconductor device, comprising:
 performing an ion implantation process into a first device region of a substrate; and   performing a first photolithography and etch process to simultaneously form a first source/drain recess for a first device in the first device region and a second source/drain recess for a second device in a second device region different than the first device region;   wherein a first depth of the first source/drain recess is greater than a second depth of the second source/drain recess.   
     
     
         2 . The method of  claim 1 , further comprising forming a first source/drain feature within the first source/drain recess and a second source/drain feature within the second source/drain recess. 
     
     
         3 . The method of  claim 1 , wherein the ion implantation process increases an etch rate of a first source/drain region of the first device. 
     
     
         4 . The method of  claim 1 , wherein the first device includes an N-type system-on-a-chip (SOC) logic device or a P-type SOC logic device, and wherein the second device includes an N-type static random-access memory (SRAM) device or a P-type SRAM device. 
     
     
         5 . The method of  claim 2 , wherein the first source/drain feature extends above a first top surface of a first fin over which the first source/drain feature is formed, and wherein the second source/drain feature extends above a second top surface of a second fin over which the second source/drain feature is formed. 
     
     
         6 . The method of  claim 1 , further comprising:
 performing a second photolithography and etch process to simultaneously form a third source/drain recess for a third device in the first device region and a fourth source/drain recess for a fourth device in the second device region;   wherein a third depth of the third source/drain recess is greater than a fourth depth of the fourth source/drain recess.   
     
     
         7 . The method of  claim 1 , wherein the ion implantation process includes performing a plurality of ion implantation processes at different implant angles, and wherein a first width of the first source/drain recess is greater than a second width of the second source/drain recess. 
     
     
         8 . The method of  claim 1 , wherein the ion implantation process further includes performing the ion implantation process into a portion of the second device region, wherein the first photolithography and etch process simultaneously forms the first source/drain recess, the second source/drain recess, and a third source/drain recess for a third device in the portion of the second device region. 
     
     
         9 . The method of  claim 8 , wherein a third depth of the third source/drain recess is both greater than the second depth of the second source/drain recess and substantially equal to the first depth of the first source/drain recess. 
     
     
         10 . A method, comprising:
 performing an ion implantation process into a memory device region or a logic device region to modify an etch rate of one of a first source/drain region within the memory device region or a second source/drain region within the logic device region; and   simultaneously etching the first source/drain region to form a first source/drain recess for a first memory device and the second source/drain region to form a second source/drain recess for a first logic device; and   forming a first source/drain feature within the first source/drain recess and a second source/drain feature within the second source/drain recess;   wherein a first depth of the first source/drain feature is different than a second depth of the second source/drain feature.   
     
     
         11 . The method of  claim 10 , wherein the ion implantation process is performed into the memory device region, and wherein the etch rate of the first source/drain region is decreased. 
     
     
         12 . The method of  claim 10 , wherein the ion implantation process is performed into the logic device region, and wherein the etch rate of the second source/drain region is increased. 
     
     
         13 . The method of  claim 10 , wherein the first depth of the first source/drain feature is less than the second depth of the second source/drain feature. 
     
     
         14 . The method of  claim 10 , wherein the ion implantation process includes performing a plurality of ion implantation processes at different implant angles, and wherein a first width of the first source/drain feature is different than a second width of the second source/drain feature. 
     
     
         15 . The method of  claim 10 , wherein the first memory device includes an N-type static random-access memory (SRAM) device or a P-type SRAM device, and wherein the first logic device includes an N-type system-on-a-chip (SOC) logic device or a P-type SOC logic device. 
     
     
         16 . A semiconductor device, comprising:
 a substrate including a first device region and a second device region;   a first gate structure disposed in the first device region and a second gate structure disposed in the second device region; and   a first source/drain feature disposed adjacent to the first gate structure and a second source/drain feature disposed adjacent to the second gate structure;   wherein a first top surface of the first source/drain feature and a second top surface of the second source/drain feature are substantially level;   wherein a first bottom surface of the first source/drain feature is a first distance away from the first top surface; and   wherein a second bottom surface of the second source/drain feature is a second distance away from the second top surface, the second distance greater than the first distance.   
     
     
         17 . The semiconductor device of  claim 16 , wherein the first device region includes a static random-access memory (SRAM) device region, and wherein the second device region includes a system-on-a-chip (SOC) logic device region. 
     
     
         18 . The semiconductor device of  claim 16 , wherein the first source/drain feature and the second source/drain feature include an N-type source/drain feature or a P-type source/drain feature. 
     
     
         19 . The semiconductor device of  claim 16 , wherein a first width of the first source/drain feature is less than a second width of the second source/drain feature. 
     
     
         20 . The semiconductor device of  claim 16 , further comprising:
 a third source/drain feature disposed adjacent to a third gate structure in the first device region;   wherein a third top surface of the third source/drain feature is substantially level with the first top surface and the second top surface; and   wherein a third bottom surface of the third source/drain feature is the second distance away from the third top surface.