Voltage supply selection circuit

Abstract

The present disclosure describes an example circuit for selecting a voltage supply. The circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and is configured to receive a second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal.

What is claimed is: 
     
         1 . A circuit, comprising:
 a first control switch configured to receive a control signal and a first voltage supply, wherein the first control switch comprises an inverter circuit configured to receive the control signal and the first voltage supply, and wherein the control signal is configured to transition from a first voltage level to a second voltage level while in a logic high state;   a first voltage supply switch electrically coupled to the first control switch and configured to receive a second voltage supply;   a second control switch configured to receive the control signal and the second voltage supply; and   a second voltage supply switch electrically coupled to the second control switch and configured to receive the first voltage supply, wherein the first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal.   
     
     
         2 . The circuit of  claim 1 , wherein the first control switch further comprises a level-shifter circuit configured to receive the control signal and the first voltage supply and electrically coupled to the inverter circuit. 
     
     
         3 . The circuit of  claim 1 , wherein the first voltage supply switch further comprises a p-type transistor configured to output the second voltage supply based on an output of the first control switch. 
     
     
         4 . The circuit of  claim 1 , wherein the second control switch comprises an other inverter circuit configured to receive the second voltage supply. 
     
     
         5 . The circuit of  claim 1 , wherein the second voltage supply switch comprises a p-type transistor configured to output the first voltage supply based on an output of the second control switch. 
     
     
         6 . The circuit of  claim 1 , wherein the first control switch comprises a first output electrically coupled to an input to the second control switch, and wherein the second control switch comprises a second output electrically coupled to an input to the first control switch. 
     
     
         7 . The circuit of  claim 1 , wherein each of the first and second control switches comprises a delay circuit. 
     
     
         8 . The circuit of  claim 7 , wherein the delay circuit comprises one or more inverter circuits. 
     
     
         9 . A circuit, comprising:
 a first control switch configured to receive a control signal and a first voltage supply;   a first voltage supply switch electrically coupled to the first control switch and configured to receive a second voltage supply;   a second control switch configured to receive the control signal and the second voltage supply, wherein the second control switch comprises a level-shifter circuit configured to receive the control signal and the first voltage supply; and   a second voltage supply switch electrically coupled to the second control switch and configured to receive the first voltage supply, wherein the first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal, and wherein the control signal is configured to transition from a first voltage level to a second voltage level while in a logic high state.   
     
     
         10 . The circuit of  claim 9 , wherein the first control switch comprises another level-shifter circuit configured to receive the control signal and the first voltage supply. 
     
     
         11 . The circuit of  claim 9 , wherein the first voltage supply switch comprises a p-type transistor configured to output the second voltage supply based on an output of the first control switch. 
     
     
         12 . The circuit of  claim 9 , wherein the second control switch further comprises an inverter circuit configured to receive the first voltage supply and electrically coupled to the level-shifter circuit. 
     
     
         13 . The circuit of  claim 9 , wherein the second control switch further comprises an inverter circuit configured to receive the second voltage supply. 
     
     
         14 . The circuit of  claim 9 , wherein the second voltage supply switch comprises a p-type transistor configured to output the first voltage supply based on an output of the second control switch. 
     
     
         15 . The circuit of  claim 9 , wherein the first control switch comprises a first output electrically coupled to an input to the second control switch, and wherein the second control switch comprises a second output electrically coupled to an input to the first control switch. 
     
     
         16 . The circuit of  claim 9 , wherein each of the first and second control switches comprises a delay circuit. 
     
     
         17 . A method, comprising:
 receiving, with a first switch, a selection signal and a first voltage, wherein the first switch comprises an inverter circuit configured to receive the control signal and the first voltage supply, and wherein the control signal is configured to transition from a first voltage level to a second voltage level while in a logic high state;   receiving, with a second switch, a second voltage;   receiving, with a third switch, the selection signal and the second voltage;   receiving, with a fourth switch, the first voltage; and   transitioning a voltage supply from the first voltage to the second voltage in response to the selection signal transitioning from a first logic level to a second logic level and in response to the first and second voltages being substantially at the same voltage level.   
     
     
         18 . The method of  claim 17 , wherein receiving the selection signal and the first voltage comprises receiving, with the first switch, an output of the third switch. 
     
     
         19 . The method of  claim 17 , wherein receiving the selection signal and the second voltage comprises receiving, with the third switch, an output of the first switch. 
     
     
         20 . The method of  claim 17 , wherein receiving the selection signal and the first voltage and receiving the selection signal and the second voltage comprise activating or de-activating the third and fourth switches concurrently for a period of time.