Heat sink layout designs for advanced finfet integrated circuits

Abstract

A method of making a semiconductor device includes forming an active device region in a substrate. The method further includes forming a first transistor in the active device region, the first transistor including a first channel region a first source region and a first drain region. The method further includes forming a guard ring region outside the active device region. The method further includes forming a second transistor in the guard ring region, the second transistor comprising a second channel region a second source region and a second drain region. The second channel region includes a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region.

What is claimed is: 
     
         1 . A method of making a semiconductor device, the method comprising:
 forming an active device region in a substrate;   forming a first transistor in the active device region, the first transistor comprising a first channel region a first source region and a first drain region; and   forming a guard ring region outside the active device region;   forming a second transistor in the guard ring region, the second transistor comprising a second channel region a second source region and a second drain region,   wherein the second channel region comprises a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region.   
     
     
         2 . The method of  claim 1 , further comprises electrically connecting the first source region to the second source region. 
     
     
         3 . The method of  claim 1 , wherein forming the first transistor comprises forming a fin field effect transistor (FinFET). 
     
     
         4 . The method of  claim 1 , further comprising forming a source contact structure over the first source region and the second source region. 
     
     
         5 . The method of  claim 4 , wherein forming the source contact structure comprises forming the source contact structure as a continuous layer. 
     
     
         6 . The method of  claim 1 , further comprising forming a first gate structure over the first channel region. 
     
     
         7 . The method of  claim 6 , further comprising forming a second gate structure over the second channel region. 
     
     
         8 . The method of  claim 1 , wherein forming the second transistor comprises forming the second transistor spaced from the first transistor in a first direction parallel to a top surface of the substrate. 
     
     
         9 . The method of  claim 8 , wherein forming the second transistor comprises forming the second source region offset from the first source region in a second direction, and the second direction is perpendicular to the first direction. 
     
     
         10 . The method of  claim 8 , wherein forming the second transistor comprises forming the second source region aligned with the first channel region in the first direction. 
     
     
         11 . A method of forming a semiconductor device, the method comprising:
 forming a first transistor in an active device region, wherein the first transistor comprises a first channel region,   forming a second transistor in a guard ring region, wherein the second transistor comprises a second channel region, and a thermal conductivity of the second channel region is greater than a thermal conductivity of the first channel region.   
     
     
         12 . The method of  claim 11 , wherein forming the first transistor comprises doping the first channel region to have a first dopant concentration, and forming the second transistor comprises doping the second channel region to have a second dopant concentration less than the first dopant concentration. 
     
     
         13 . The method of  claim 11 , wherein forming the first transistor comprises forming the first channel region comprising SiGe. 
     
     
         14 . The method of  claim 13 , wherein forming the second transistor comprises forming the second channel region comprising Si. 
     
     
         15 . The method of  claim 11 , wherein forming the second transistor comprises forming an inactive device. 
     
     
         16 . A method of making a semiconductor device, the method comprising:
 forming an active device region in a substrate;   forming a transistor in the active device region, the transistor comprising a channel region and a source/drain (S/D) region;   defining a passive device region in the substrate;   forming a resistor in the passive device region;   forming a contact structure overlying the S/D region; and   forming an interconnect layer electrically coupling the contact structure and a first terminal of the resistor, wherein a second terminal of the resistor is floating.   
     
     
         17 . The method of  claim 16 , wherein forming the resistor comprises:
 forming a doped well in the passive device region; and   forming a highly doped well in the doped well.   
     
     
         18 . The method of  claim 17 , wherein forming the interconnect layer comprises electrically connecting the contact structure to the highly doped well. 
     
     
         19 . The method of  claim 16 , wherein forming the resistor comprises forming the resistor on an opposite side of the S/D region from the channel region. 
     
     
         20 . The method of  claim 16 , further comprising:
 forming a second resistor on an opposite side of the transistor from the resistor; and   electrically connecting the S/D region to the second resistor.