Semiconductor memory device with 3d structure

Abstract

A semiconductor memory device with a three-dimensional (3D) structure may include: a cell region arranged over a substrate, including a cell structure; a peripheral circuit region arranged between the substrate and the cell region; an upper wiring structure arranged over the cell region; main channel films and dummy channel films formed through the cell structure. The dummy channel films are suitable for electrically coupling the upper wiring structure.

What is claimed is: 
     
         1 . A semiconductor memory device with a three-dimensional (3D) structure, comprising:
 a cell region arranged over a substrate, including a cell structure, wherein the cell structure includes a plurality of cell gate conductive films and a plurality of insulation films alternately stacked over the substrate;   a peripheral circuit region arranged between the substrate and the cell region;   an upper wiring structure arranged over the cell region;   main channel films and dummy channel films formed through the cell structure, wherein the dummy channel films are suitable for electrically coupling the upper wiring structure and the peripheral circuit region,   wherein the main channel films and the dummy channel films extend above an uppermost film of the plurality of cell gate conductive films and the plurality of insulation films of the cell structure relative to the substrate,   wherein the peripheral circuit region comprises:   peripheral circuit elements; and   a lower wiring structure suitable for electrically coupling the peripheral circuit elements and the dummy channel films,   wherein the peripheral circuit elements comprise a first peripheral circuit element and a second peripheral circuit element suitable for receiving a signal outputted from the first peripheral circuit element, and   wherein the dummy channel films comprise:   a first dummy channel film suitable for electrically coupling the first peripheral circuit element and the upper wiring structure; and   a second dummy channel film suitable for electrically coupling the second peripheral circuit element and the upper wiring structure.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein the upper wiring structure comprises:
 a first dummy bit line electrically coupled to the first dummy channel film;   a second dummy bit line electrically coupled to the second dummy channel film; and   an upper wiring layer disposed over the first and second dummy bit lines, suitable for electrically coupling the first and second dummy bit lines.   
     
     
         3 . The semiconductor memory device of  claim 2 , wherein the upper wiring layer is extended in a direction perpendicular to the bit lines and the first and second dummy bit lines. 
     
     
         4 . The semiconductor memory device of  claim 2 , wherein the upper wiring layer comprises a fuse. 
     
     
         5 . A semiconductor memory device with a three-dimensional (3D) structure, comprising:
 a cell region arranged over a substrate, including a cell structure, wherein the cell structure includes a plurality of cell gate conductive films and a plurality of insulation films alternately stacked over the substrate;   a peripheral circuit region disposed between the substrate and the cell region;   main channel films formed through the cell structure;   first and second dummy channel films electrically coupled to the peripheral circuit region through the cell structure; and   a fuse disposed over the cell region and coupled between the first and second dummy channel films,   wherein the main channel films and the first and second dummy channel films extend above an uppermost film of the plurality of cell gate conductive films and the plurality of insulation films of the cell structure relative to the substrate.   
     
     
         6 . A semiconductor memory device with a three-dimensional (3D) structure, comprising:
 a cell region arranged over a substrate, including a cell structure,   a peripheral circuit region disposed between the substrate and the cell region;   main channel films formed through the cell structure;   first and second dummy channel films electrically coupled to the peripheral circuit region through the cell structure;   a fuse disposed over the cell region and coupled between the first and second dummy channel films; and   a fuse control circuit formed in the peripheral circuit region which cuts the fuse and verifies the cut state of the fuse.