Namespaces allocation in non-volatile memory devices

Abstract

A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: receive, via the host interface, a request from a host to allocate a namespace of a quantity of non-volatile memory; generate, in response to the request, a namespace map identifying a plurality of blocks of addresses having a same predetermined block size, and a partial block of addresses having a size smaller than the predetermined block size; and convert, using the namespace map, logical addresses in the namespace communicated from the host to physical addresses for the quantity of the non-volatile memory. For example, the request for allocating the namespace can be in accordance with an NVMe protocol.

What is claimed is: 
     
         1 . A device, comprising:
 a memory; and   a circuit configured to translate, based on a plurality of block sizes, first logical addresses specified in first storage spaces defined in portions of the memory into second logical addresses specified in a second storage space defined in the memory.   
     
     
         2 . The device of  claim 1 , wherein the first storage spaces include a namespace allocated from a storage capacity of the memory. 
     
     
         3 . The device of  claim 2 , wherein the second storage space includes the storage capacity. 
     
     
         4 . The device of  claim 1 , wherein the circuit is configured to divide, according to the plurality of block sizes, the first logical addresses in the first storage spaces into first blocks and map the first blocks into second blocks in the second storage space. 
     
     
         5 . The device of  claim 4 , wherein the first blocks include third logical addresses that are specified continuously in one of the first storage spaces; and fourth logical addresses, mapped from the third logical addresses, are not continuous in the second storage space. 
     
     
         6 . The device of  claim 5 , wherein the plurality of block sizes include a common block size shared across the first storage spaces in division of the first logical addresses in the first storage spaces into the first blocks. 
     
     
         7 . The device of  claim 6 , wherein each of the first storage spaces is divided by no more than two block sizes;
 wherein each of the first storage spaces is divided by at least one block size that is no larger than the common block size; and   wherein each of the first storage spaces is divided to include no more than one block of logical addresses having a block size that is different from the common block size.   
     
     
         8 . The device of  claim 7 , wherein the circuit is configured at least in part via firmware. 
     
     
         9 . The device of  claim 7 , wherein the circuit is configured to consolidate at least two of the first blocks into being mapped within a third block having the common block size in the second storage space. 
     
     
         10 . A method, comprising:
 allocating a plurality of first storage spaces respectively from a plurality of portions of a memory of a device; and   translating, by the device based on a plurality of block sizes, first logical addresses specified in the first storage spaces into second logical addresses specified in a second storage space defined in the memory.   
     
     
         11 . The method of  claim 10 , further comprising:
 dividing, according to the plurality of block sizes, the first logical addresses in the first storage spaces into first blocks to map the first blocks into second blocks in the second storage space.   
     
     
         12 . The method of  claim 11 , wherein the first blocks include third logical addresses that are specified continuously in one of the first storage spaces; and fourth logical addresses, mapped from the third logical addresses, are not continuous in the second storage space. 
     
     
         13 . The method of  claim 12 , wherein the plurality of block sizes include a common block size shared across the first storage spaces in division of the first logical addresses in the first storage spaces into the first blocks. 
     
     
         14 . The method of  claim 13 , wherein each of the first storage spaces is divided by no more than two block sizes;
 wherein each of the first storage spaces is divided by at least one block size that is no larger than the common block size; and   wherein each of the first storage spaces is divided to include no more than one block of logical addresses having a block size that is different from the common block size.   
     
     
         15 . The method of  claim 14 , wherein the first storage spaces include a namespace allocated from a storage capacity of the memory; and the second storage space includes the storage capacity. 
     
     
         16 . The method of  claim 14 , further comprising:
 consolidating, at least two of the first blocks into being mapped within a third block having the common block size in the second storage space.   
     
     
         17 . A non-transitory computer storage medium storing instructions which, when executed by a device having a memory, cause the device to perform a method, the method comprising:
 allocating a plurality of first storage spaces respectively from a plurality of portions of the memory of the device; and   translating, by the device based on a plurality of block sizes, first logical addresses specified in the first storage spaces into second logical addresses specified in a second storage space defined in the memory.   
     
     
         18 . The non-transitory computer storage medium of  claim 17 , wherein the method further comprises:
 dividing, according to the plurality of block sizes, the first logical addresses in the first storage spaces into first blocks to map the first blocks into second blocks in the second storage space.   
     
     
         19 . The non-transitory computer storage medium of  claim 18 , wherein the first blocks include third logical addresses that are specified continuously in one of the first storage spaces; and fourth logical addresses, mapped from the third logical addresses, are not continuous in the second storage space; and
 wherein the plurality of block sizes include a common block size shared across the first storage spaces in division of the first logical addresses in the first storage spaces into the first blocks.   
     
     
         20 . The non-transitory computer storage medium of  claim 19 , wherein each of the first storage spaces is divided by no more than two block sizes;
 wherein each of the first storage spaces is divided by at least one block size that is no larger than the common block size;   wherein each of the first storage spaces is divided to include no more than one block of logical addresses having a block size that is different from the common block size; and   wherein the method further comprises:
 consolidating, at least two of the first blocks into being mapped within a third block having the common block size in the second storage space.