Buffer circuits and semiconductor structures thereof

Abstract

A buffer circuit is provided to output an output signal at an output node. The buffer circuit includes first and second inverters and first and second switches. The first inverter inverts an input signal. The second inverter is coupled between the first inverter and the output node. The first switch is coupled between a first voltage source terminal and the output node. The second switch is coupled between the output node and a second voltage source terminal. First and second voltages are respectively provided to the first and second voltage source terminals. In response to the input signal switching to a first level from a second level, the first switch is turned on to pre-charge the output node. In response to the input signal transiting to the second level from the first level, the second switch is turned on to pre-discharge the output node.

What is claimed is: 
     
         1 . A buffer circuit for receiving an input signal at an input node and outputting an output signal at an output node, comprising:
 a first inverter, coupled to the input node to receive the input signal, inverting the input signal to generate an inverted input signal;   a second inverter having an input terminal receiving the inverted input signal and an output terminal coupled to the output node;   a first switch coupled between a first voltage source terminal and the output node and controlled by the input signal; and   a second switch coupled between the output node and a second voltage source terminal and controlled by the input signal,   wherein a first voltage is provided to the first voltage source terminal, and a second voltage is provided to the second voltage source terminal,   in response to the input signal switching to a first level from a second level, the first switch is turned on to pre-charge the output node toward the first voltage, and   in response to the input signal transiting to the second level from the first level, the second switch is turned on to pre-discharge the output node toward the second voltage.   
     
     
         2 . The buffer circuit as claimed in  claim 1 , wherein:
 the first switch comprises a first N-type transistor having a gate electrode coupled to the input node, a first drain/source electrode coupled to the first voltage source terminal, and a second drain/source electrode coupled to the output node, and   the second switch comprises a first P-type transistor having a gate electrode coupled to the input node, a first drain/source electrode coupled to the output node, and a second drain/source electrode coupled to the second voltage source terminal.   
     
     
         3 . The buffer circuit as claimed in  claim 2 , wherein the first voltage provided to the first voltage source terminal is higher than the second voltage provided to the second voltage source terminal. 
     
     
         4 . The buffer as claimed in  claim 2 , wherein:
 the second inverter comprises a second N-type transistor controlled by the inverted input signal and a second P-type transistor controlled by the inverted input signal,   the first N-type transistor and the second P-type transistor are coupled in parallel between the first voltage source terminal and the output node to form a first transmission gate,   the first P-type transistor and the second N-type transistor are coupled in parallel between the second voltage source terminal and the output node to form a second transmission gate.   
     
     
         5 . The buffer as claimed in  claim 4 , wherein:
 in response to the first level of the input signal, the first transmission gate passes the first voltage to the output node, and   in response to the second level of the input signal, the second transmission gate passes the second voltage to the output node.   
     
     
         6 . The buffer circuit as claimed in  claim 3 , wherein the first and second N-type transistors and the first and second P-type transistors are metal-oxide-semiconductor (MOS) transistors. 
     
     
         7 . The buffer circuit as claimed in  claim 2 , wherein the second inverter comprises:
 a second P-type transistor having a gate electrode coupled to the input terminal of the second inverter for receiving the inverted input signal, a first drain/source electrode coupled to the first voltage source terminal, and a second drain/source electrode coupled to the output node; and   a second N-type transistor having a gate electrode coupled to the input terminal of the second inverter for receiving the inverted input signal, a first drain/source electrode coupled to the output node, and a second drain/source electrode coupled to the second voltage source terminal.   
     
     
         8 . The buffer circuit as claimed in  claim 2 , wherein the first N-type transistor and the first P-type transistor are metal-oxide-semiconductor (MOS) transistors. 
     
     
         9 . The buffer circuit as claimed in  claim 1 , wherein the first voltage provided to the first voltage source terminal is higher than the second voltage provided to the second voltage source terminal. 
     
     
         10 . A semiconductor structure of a buffer circuit, comprising:
 a substrate;   a P-type diffusion region formed on the substrate and extending parallel to a first direction;   an N-type diffusion region formed on the substrate, spaced apart from the P-type diffusion region, and extending parallel to the first direction;   a first polysilicon region formed above the P-type and N-type diffusion regions and extending parallel to a second direction and across the P-type and N-type diffusion regions, wherein the first direction is perpendicular to the second direction;   a first conductive segment extending parallel to the first direction; and   a second conductive segment spaced apart from the first conductive segment and extending parallel to the first direction,   wherein the P-type diffusion region comprises a first P-type diffusion portion disposed on a first side of the first polysilicon region, and the first P-type diffusion portion is electrically connected to the second conductive segment,   wherein the N-type diffusion region comprises a first N-type diffusion portion disposed on the first side of the first poly region, and the first N-type diffusion portion is electrically connected to the first conductive segment, and   wherein a first voltage provided to the first conductive segment is higher than a second voltage provided to the second conductive segment.   
     
     
         11 . The semiconductor structure as claimed in  claim 10 , further comprising:
 a third conductive segment formed above the P-type diffusion region and extending parallel to the first direction; and   a fourth conductive segment formed above the third conductive segment and extending parallel to the second direction,   wherein the third conductive segment comprises a first end electrically connected to the first P-type diffusion portion and a second end, and   wherein the fourth conductive segment comprises a first end electrically connected to the second end of the third conductive segment and a second end electrically connected to the second conductive segment.   
     
     
         12 . The semiconductor structure as claimed in  claim 10 , further comprising:
 a third conductive segment formed above the N-type diffusion region and extending parallel to the first direction; and   a fourth conductive segment formed above the third conductive segment and extending parallel to the second direction,   wherein the third conductive segment comprises a first end electrically connected to the first N-type diffusion portion and a second end, and   wherein the fourth conductive segment comprises a first end electrically connected to the second end of the third conductive segment and a second end electrically connected to the first conductive segment.   
     
     
         13 . The semiconductor structure as claimed in  claim 10 , further comprising:
 a second polysilicon region formed above the first and second diffusion regions and extending parallel to the second direction and across the P-type and N-type diffusion regions; and   a third polysilicon region formed above the first and second diffusion regions and extending parallel to the second direction and across the P-type and N-type diffusion regions,   wherein the third polysilicon region is disposed between the first and second polysilicon regions,   wherein the P-type diffusion region comprises a second P-type diffusion portion disposed between the second and third polysilicon regions, and the second P-type diffusion portion is electrically connected to the first conductive segment, and   wherein the N-type diffusion region comprises a second N-type diffusion portion disposed between the second and third polysilicon regions, and the second N-type diffusion portion is electrically connected to the second conductive segment.   
     
     
         14 . The semiconductor structure as claimed in  claim 13 , further comprising:
 a third conductive segment formed under the P-type diffusion region and the first conductive segment and extending parallel to the second direction; and   a fourth conductive segment formed under the N-type diffusion region and the second conductive segment and extending parallel to the second direction,   wherein the third conductive segment electrically connects the first conductive segment to the second P-type diffusion portion, and the fourth conductive segment electrically connects the second conductive segment to the second N-type diffusion portion.   
     
     
         15 . The semiconductor structure as claimed in  claim 13 , wherein:
 an input signal of the buffer circuit is applied to the first polysilicon region and the second polysilicon region, and   a signal that is inverse to the input signal is applied to the third polysilicon region.   
     
     
         16 . The semiconductor structure as claimed in  claim 13 , wherein:
 the P-type diffusion region comprises a third P-type diffusion portion disposed between the first and third polysilicon regions,   the N-type diffusion region comprises a third N-type diffusion portion disposed between the first and third polysilicon regions, and   the third P-type diffusion portion is electrically connected to the third N-type diffusion portion.   
     
     
         17 . The semiconductor structure as claimed in  claim 16 , further comprising:
 a third conductive segment formed under the P-type diffusion region and the N-type diffusion region and extending parallel to the second direction;   wherein the third conductive segment electrically connects the third P-type diffusion portion to the third N-type diffusion portion, and   wherein the third conductive segment is electrically connected to an output node of the buffer circuit.   
     
     
         18 . The semiconductor structure as claimed in  claim 13 , wherein:
 the P-type diffusion region comprises a third P-type diffusion portion, and the second and third P-type diffusion portions are disposed on two sides of the second polysilicon region respectively,   the N-type diffusion region comprises a third N-type diffusion portion, and the second and third N-type diffusion portions are disposed on two sides of the second polysilicon region respectively, and   the third P-type diffusion portion is electrically connected to the third N-type diffusion portion and the third polysilicon region.   
     
     
         19 . The semiconductor structure as claimed in  claim 18 , further comprising:
 a third conductive segment formed under the P-type diffusion region and the N-type diffusion region and extending parallel to the second direction; and   a fourth conductive segment formed above the third conductive segment and extending parallel to the first direction,   wherein the third conductive segment electrically connects the third P-type diffusion portion to the third N-type diffusion portion, and   wherein the fourth conductive segment electrically connects the third conductive segment to the third polysilicon region.   
     
     
         20 . The semiconductor structure as claimed in  claim 10 , wherein an input signal of the buffer circuit is applied to the first polysilicon region.