Replacement metal gates to enhance transistor strain

Abstract

Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.

What is claimed is: 
     
         1 . An integrated circuit structure, comprising:
 an NMOS transistor, comprising:
 a first gate structure over a substrate, the substrate comprising silicon, and the first gate structure comprising: 
 a gate dielectric layer comprising hafnium and oxygen; 
 an n-type material layer over the gate dielectric layer, the n-type material layer comprising aluminum, titanium and carbon; 
 a p-type material layer over the n-type material layer; and 
 a conductive fill material over the p-type material layer, the conductive fill material comprising tungsten; and 
 a first epitaxial n-type source or drain region adjacent to a first side of the first gate structure; and 
 a second epitaxial n-type source or drain region adjacent to a second side of the first gate structure, the second side opposite the first side, the first and second epitaxial n-type source or drain regions having a first vertical thickness; and 
   a PMOS transistor, comprising:
 a second gate structure over the substrate, the second gate structure comprising a gate electrode and a gate dielectric layer; 
 a first epitaxial p-type source or drain region adjacent to a first side of the second gate structure; and 
 a second epitaxial p-type source or drain region adjacent to a second side of the second gate structure, the second side opposite the first side, the first and second epitaxial p-type source or drain regions having a second vertical thickness greater than the first vertical thickness, the first and second epitaxial p-type source or drain regions having a bottommost surface below a bottommost surface of the second gate structure, and the first and second epitaxial p-type source or drain regions having an uppermost surface above an uppermost surface of the gate electrode of the second gate structure. 
   
     
     
         2 . The integrated circuit structure of  claim 1 , wherein the p-type material layer is directly on the n-type material layer. 
     
     
         3 . The integrated circuit structure of  claim 1 , wherein the conductive fill material is directly on the p-type material layer. 
     
     
         4 . The integrated circuit structure of  claim 1 , wherein the p-type material layer is directly on the n-type material layer, and wherein the conductive fill material is directly on the p-type material layer. 
     
     
         5 . The integrated circuit structure of  claim 1 , wherein the n-type material layer is directly on the gate dielectric layer. 
     
     
         6 . The integrated circuit structure of  claim 1 , wherein the n-type material layer is a carbide layer. 
     
     
         7 . The integrated circuit structure of  claim 1 , further comprising a tensile strained channel between the first epitaxial n-type source or drain region and the second epitaxial n-type source or drain region. 
     
     
         8 . The integrated circuit structure of  claim 1 , wherein the p-type material layer comprises ruthenium. 
     
     
         9 . The integrated circuit structure of  claim 1 , wherein the p-type material layer comprises palladium. 
     
     
         10 . The integrated circuit structure of  claim 1 , wherein the p-type material layer comprises platinum. 
     
     
         11 . The integrated circuit structure of  claim 1 , wherein the p-type material layer comprises cobalt. 
     
     
         12 . The integrated circuit structure of  claim 1 , wherein the p-type material layer comprises nickel. 
     
     
         13 . The integrated circuit structure of  claim 1 , wherein the gate dielectric layer is a U-shaped gate dielectric layer. 
     
     
         14 . The integrated circuit structure of  claim 1 , wherein the n-type material layer is a U-shaped n-type material layer. 
     
     
         15 . The integrated circuit structure of  claim 1 , wherein the p-type material layer is a U-shaped p-type material layer. 
     
     
         16 . The integrated circuit structure of  claim 1 , further comprising a dielectric spacer along the first and second sides of the first gate structure. 
     
     
         17 . The integrated circuit structure of  claim 16 , wherein the dielectric spacer comprises silicon and nitrogen. 
     
     
         18 . The integrated circuit structure of  claim 1 , further comprising halo implants. 
     
     
         19 . The integrated circuit structure of  claim 1 , further comprising tip implants. 
     
     
         20 . The integrated circuit structure of  claim 1 , further comprising halo implants and tip implants.