Esd protection circuit and semiconductor device

Abstract

An ESD protection circuit is connected in parallel with an internal circuit operating at a predetermined operating voltage between a V DD terminal and a V SS terminal, and includes an NMOS transistor in which an N type high concentration drain region is connected to the V DD terminal and an N type high concentration source region is connected to the V SS terminal. A threshold voltage and a trigger voltage of a parasitic bipolar transistor of the NMOS transistor are higher than the operating voltage and lower than a breakdown voltage of the internal circuit and a breakdown voltage of a gate insulating film of the NMOS transistor.

What is claimed is: 
     
         1 . An ESD protection circuit, connected in parallel with a protected circuit operating at a predetermined operating voltage between a first terminal and a second terminal, wherein the ESD protection circuit comprises:
 an NMOS transistor, in which at least a drain is connected to the first terminal and a source is connected to the second terminal, wherein   a threshold voltage and a trigger voltage of a parasitic bipolar transistor of the NMOS transistor are higher than the operating voltage and lower than a breakdown voltage of the protected circuit and a gate insulating film.   
     
     
         2 . The ESD protection circuit according to  claim 1 , wherein
 a gate of the NMOS transistor is connected to the first terminal.   
     
     
         3 . The ESD protection circuit according to  claim 2 , wherein
 a resistive element is connected between the first terminal and the gate of the NMOS transistor.   
     
     
         4 . The ESD protection circuit according to  claim 3 , wherein
 a diode having an avalanche breakdown voltage higher than the operating voltage is connected between the second terminal and the gate of the NMOS transistor.   
     
     
         5 . The ESD protection circuit according to  claim 1 , wherein
 a gate of the NMOS transistor is in a floating state.   
     
     
         6 . The ESD protection circuit according to  claim 1 , wherein
 the NMOS transistor comprises:
 a semiconductor substrate; 
 a P type well region, formed on a surface side of the semiconductor substrate; 
 an N type high concentration drain region and an N type high concentration source region, provided spaced apart over an upper part of the P type well region and having a higher impurity concentration than an impurity concentration of the P type well region; 
 a P type intermediate concentration region, provided in a region in contact with at least the N-type high concentration drain region and having a higher P type impurity concentration than the impurity concentration of the P type well region; 
 a gate insulating film, provided on a semiconductor surface between the N type high concentration drain region and the N type high concentration source region; and 
 a gate electrode, provided on the gate insulating film. 
   
     
     
         7 . The ESD protection circuit according to  claim 6 , wherein
 the P type intermediate concentration region is further in contact with the P type well region.   
     
     
         8 . The ESD protection circuit according to  claim 6 , wherein
 the P type intermediate concentration region is further provided in a channel region between the N type high concentration drain region and the N type high concentration source region.   
     
     
         9 . The ESD protection circuit according to  claim 8 , wherein
 a P type intermediate concentration channel region is provided on a surface of the semiconductor substrate between the N type high concentration drain region and the N type high concentration source region.   
     
     
         10 . The ESD protection circuit according to  claim 6 , wherein
 the NMOS transistor further comprises a DDD structure.   
     
     
         11 . The ESD protection circuit according to  claim 6 , wherein
 the NMOS transistor further comprises an LDD structure.   
     
     
         12 . The ESD protection circuit according to  claim 6 , wherein
 the NMOS transistor further comprises a sidewall spacer provided on a sidewall of the gate insulating film and a sidewall of the gate electrode.   
     
     
         13 . A semiconductor device, wherein
 the ESD protection circuit according to  claim 1  and a protected circuit protected from electrostatic discharge by the ESD protection circuit are connected in parallel.