US2023307413A1PendingUtilityA1

Methods for multi-wafer stacking and dicing

Assignee: YANGTZE MEMORY TECH CO LTDPriority: Jan 7, 2020Filed: Jun 2, 2023Published: Sep 28, 2023
Est. expiryJan 7, 2040(~13.4 yrs left)· nominal 20-yr term from priority
Inventors:Jialan He
H10W 72/551H10W 90/754H10W 90/20H10W 72/0198H10W 72/879H10W 72/952H10W 72/59H10W 90/00H10W 72/20H10W 72/072H10W 80/327H10W 80/312H10W 72/951H10W 80/00H10W 72/247H10W 72/07254H10W 72/252H10W 90/792H10P 54/00H10W 80/211H10P 72/7416H10P 72/74H01L 24/80H01L 21/78H01L 24/08H01L 25/0657H01L 25/18H01L 25/50H01L 2224/08145H01L 2224/80006H01L 2224/80895H01L 2224/80896H01L 2225/06524H01L 2924/1436H01L 2924/1437H01L 2924/14511
64
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

In some implementations, a structure including a carrier wafer, and a first device wafer on the carrier wafer is provided. First ablation structures are formed in the structure. The first ablation structures extend through the first device wafer. A second device wafer is bonded on the first device wafer having the first ablation structures.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method, comprising:
 providing a structure comprising a carrier wafer, and a first device wafer on the carrier wafer;   forming first ablation structures in the structure, the first ablation structures extending through the first device wafer; and   bonding a second device wafer on the first device wafer having the first ablation structures.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming an adhesion layer between the carrier wafer and the first device wafer.   
     
     
         3 . The method of  claim 2 , wherein forming the first ablation structures extending through the first device wafer, the adhesion layer and a portion of the carrier wafer. 
     
     
         4 . The method of  claim 1 , wherein the first device wafer comprises first dies, each pair of adjacent first dies being separated by one of the first ablation structures. 
     
     
         5 . The method of  claim 1 , wherein the first device wafer comprises a first side of the first device wafer and a second side of the first device wafer opposite to the first side of the first device wafer, the first side of the first device wafer being in contact with the carrier wafer, and the second side of the first device wafer comprising first bonding contacts configured to be bonded to the second device wafer. 
     
     
         6 . The method of  claim 5 , further comprising:
 thinning the first device wafer; and   forming the first bonding contacts on the second side of the first device wafer after the first device wafer is thinned.   
     
     
         7 . The method of  claim 6 , further comprising:
 bonding the second device wafer to the first device wafer in a face-to-face manner through the first bonding contacts.   
     
     
         8 . The method of  claim 5 , further comprising:
 forming second ablation structures in the second device wafer according to the first ablation structures, the second ablation structures extending through a portion of the second device wafer,   wherein at least a majority of a cross-section of the second ablation structures overlaps with a cross-section of the first ablation structures when overlaying a cross-section of the carrier wafer having the cross-section of the first ablation structures and a cross-section of the second device wafer having the cross-section of the second ablation structures.   
     
     
         9 . The method of  claim 8 , further comprising:
 providing separated bonded semiconductor devices by dicing through at least the carrier wafer, the first device wafer and the second device wafer along at least the first ablation structures and the second ablation structures,   wherein each of the separated bonded semiconductor devices comprises a die from each of the first device wafer and the second device wafer.   
     
     
         10 . A semiconductor structure, comprising:
 a carrier wafer,   a first device wafer on the carrier wafer;   first ablation structures in the first device wafer and extending through the first device wafer; and   a second device wafer on the first device wafer having the first ablation structures.   
     
     
         11 . The semiconductor structure of  claim 10 , wherein the first device wafer comprises first dies, each pair of adjacent first dies being separated by one of the first ablation structures. 
     
     
         12 . The semiconductor structure of  claim 10 , further comprising:
 an adhesion layer between the carrier wafer and the first device wafer,   wherein the first ablation structures extending through the adhesion layer and a portion of the carrier wafer.   
     
     
         13 . The semiconductor structure of  claim 12 , wherein each of the first ablation structures has a portion inside the carrier wafer with a depth no greater than one half of a thickness of the carrier wafer. 
     
     
         14 . The semiconductor structure of  claim 11 , further comprising:
 second ablation structures in the second device wafer according to the first ablation structures, the second ablation structures extending through a portion of the second device wafer that is away from the first device wafer.   
     
     
         15 . The semiconductor structure of  claim 14 , wherein the first device wafer comprises a first side of the first device wafer and a second side of the first device wafer opposite to the first side of the first device wafer, the first side of the first device wafer being in contact with the carrier wafer, and the second side of the first device wafer comprising first bonding contacts configured to be bonded to the second device wafer. 
     
     
         16 . The semiconductor structure of  claim 15 , wherein
 the second device wafer comprises second dies, each pair of adjacent second dies being separated by one of the second ablation structures; and   each second die and each corresponding first die are electrically connected by the first bonding contacts.   
     
     
         17 . The semiconductor structure of  claim 16 , wherein each of the first ablation structures has a portion inside the carrier wafer with a depth no greater than one half of a thickness of the carrier wafer. 
     
     
         18 . A method, comprising:
 providing a structure comprising a carrier wafer, and a first device wafer on the carrier wafer;   bonding a second device wafer to the first device wafer in face-to-face manner; and   forming ablation structures extending through the first device wafer.   
     
     
         19 . The method of  claim 18 , further comprising:
 forming innate ablation structures extending through a portion of the carrier wafer; and   forming an adhesion layer between the carrier wafer and the first device wafer,   wherein the ablation structures overlap the innate ablation structures.   
     
     
         20 . The method of  claim 18 , wherein the first device wafer comprises first dies, each pair of adjacent first dies being separated by one of the ablation structures.

Join the waitlist — get patent alerts

Track US2023307413A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.