High thermal conductivity vias by additive processing

Abstract

An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.

What is claimed is: 
     
         1 . A method of forming an integrated circuit, comprising:
 providing a substrate comprising a semiconductor material;   forming a heat-generating component in the substrate;   forming an interconnect region above the substrate, comprising:
 forming a dielectric layer stack above the substrate; and 
 forming a thermal via in the dielectric layer stack, comprising:
 dispensing a nanoparticle ink by an additive process in the interconnect region to form a nanoparticle ink film, wherein the nanoparticle ink film includes nanoparticles and a carrier fluid, and wherein the nanoparticle ink film is free of organic binder material; and 
 inducing cohesion of the nanoparticles, thereby forming a cohered nanoparticle film. 
 
   
     
     
         2 . The method of  claim 1 , wherein forming the thermal via further comprises heating the nanoparticle ink film to remove a volatile material from the nanoparticle ink film to form a nanoparticle film, prior to inducing cohesion of the nanoparticles. 
     
     
         3 . The method of  claim 1 , wherein forming the thermal via further comprises forming a trench in the dielectric layer stack prior to forming the nanoparticle ink film, wherein the nanoparticle ink film is formed in the trench. 
     
     
         4 . The method of  claim 1 , wherein:
 the nanoparticle ink film is a first nanoparticle ink film;   the additive process is a first additive process; and   the cohered nanoparticle film is a first cohered nanoparticle film; and   forming the thermal via further comprises:
 forming a second nanoparticle ink film comprising primarily nanoparticles by a method comprising a second additive process, on the first cohered nanoparticle film; and 
 inducing cohesion of the nanoparticles in the second nanoparticle ink film, thereby forming a second cohered nanoparticle film on the first cohered nanoparticle film. 
   
     
     
         5 . The method of  claim 1 , wherein forming the interconnect region further comprises:
 forming a dielectric layer over the thermal via, wherein the dielectric layer contacts sides of the thermal via; and   planarizing the dielectric layer.   
     
     
         6 . The method of  claim 1 , wherein the nanoparticles comprise nanoparticles of a material selected from the group consisting of aluminum oxide, diamond, hexagonal boron nitride, cubic boron nitride, aluminum nitride, metal, graphene, graphene embedded in metal, graphite, graphitic carbon, and carbon nanotubes. 
     
     
         7 . The method of  claim 1 , wherein the nanoparticles comprise a metal selected from the group consisting of copper, nickel, palladium, platinum, iridium, rhodium, cerium, osmium, molybdenum and gold, and wherein forming the thermal via further comprises forming a layer of graphitic material by a plasma enhanced chemical vapor deposition (PECVD) process on the cohered nanoparticle film. 
     
     
         8 . The method of  claim 1 , wherein the additive process comprises a process selected from the group consisting of a discrete droplet dispensing process, a continuous extrusion process, a direct laser transfer process, an electrostatic deposition process, and an electrochemical deposition process. 
     
     
         9 . The method of  claim 1 , wherein:
 the thermal via is a first thermal via;   the nanoparticle ink film is a first nanoparticle ink film;   the additive process is a first additive process;   the cohered nanoparticle film is a first cohered nanoparticle film; and   forming the interconnect region further comprises:
 forming a second thermal via in the dielectric layer stack above the first thermal via, comprising:
 dispensing a second nanoparticle ink by a second additive process in the interconnect region above the first thermal via to form a second nanoparticle ink film, wherein the second nanoparticle ink film includes nanoparticles and a carrier fluid, and wherein the second nanoparticle ink film is free of organic binder material; and 
 inducing cohesion of the nanoparticles in the second nanoparticle ink film, thereby forming a second cohered nanoparticle film that is in contact with the first thermal via. 
 
   
     
     
         10 . The method of  claim 1 , wherein inducing cohesion of the nanoparticles comprises a process selected from the group consisting of a scanned laser heating process, a flash heating process and a spike heating process. 
     
     
         11 . A method of forming an integrated circuit, comprising:
 forming an interconnect region comprising a dielectric layer stack comprising dielectric materials over a semiconductor substrate;   forming a component extending into the substrate that is configured to generate heat when operating; and   forming a thermal via within the interconnect region, the thermal via landing on a field oxide region located over the substrate, wherein the thermal via includes a cohered nanoparticle film including nanoparticles, wherein the thermal via has a thermal conductivity higher than dielectric materials touching the thermal via.   
     
     
         12 . The method of  claim 11 , wherein the cohered nanoparticle film comprises electrically non-conductive nanoparticles of a material selected from the group consisting of aluminum oxide, diamond, hexagonal boron nitride, cubic boron nitride, and aluminum nitride. 
     
     
         13 . The method of  claim 11 , wherein the cohered nanoparticle film comprises electrically conductive nanoparticles of a material selected from the group consisting of metal, graphene, graphene embedded in metal, graphite, graphitic carbon, and carbon nanotubes. 
     
     
         14 . The method of  claim 11 , wherein the cohered nanoparticle film comprises nanoparticles which include a metal selected from the group consisting of copper, nickel, palladium, platinum, iridium, rhodium, cerium, osmium, molybdenum and/or gold, and wherein the thermal via comprises a layer of graphitic material disposed on the cohered nanoparticle film. 
     
     
         15 . The method of  claim 11 , wherein the thermal via is a first thermal via and further comprising forming a second thermal via within the interconnect region above the first thermal via, wherein the second thermal via includes a cohered nanoparticle film that includes nanoparticles, and wherein the second thermal via has a thermal conductivity higher than dielectric materials touching the second thermal via. 
     
     
         16 . The method of  claim 15 , wherein the second thermal via contacts the first thermal via. 
     
     
         17 . The method of  claim 15 , further comprising forming a non-circuit interconnect between the first thermal via and the second thermal via, wherein the second thermal via contacts the non-circuit interconnect and the first thermal via contacts the non-circuit interconnect. 
     
     
         18 . The method of  claim 11 , wherein the thermal via contacts a first interconnect and a second interconnect, the first interconnect being electrically isolated from the second interconnect. 
     
     
         19 . The method of  claim 11 , wherein the thermal via extends proximate to matching components of the integrated circuit. 
     
     
         20 . A method of forming an integrated circuit, comprising:
 forming an interconnect region over a semiconductor substrate, the interconnect region having a dielectric layer stack including dielectric materials;   forming a component that extends into the substrate and is configured to generate heat when operating; and   forming a thermal via within the interconnect region that lands on a field oxide region that extends below a surface of the substrate.